Abstract: There is provided a mask guide including a guide positioned between a mask and a chin of a user to prevent the user's chin and an inner surface of the mask from coming in contact with each other. The guide includes a first guide disposed on the inner surface of the mask. The guide includes a second guide configured to be positioned on the user's chin and configured to be moved in accordance with movement of the user's chin.

Abstract: A display apparatus comprises a substrate including a plurality of sub-pixels, a thin film transistor and a display device disposed in each of the sub-pixels over the substrate, and a plurality of capacitor disposed in parallel on same plane in the sub-pixel.

Abstract: There is provided a mask guide including a guide positioned between a mask and a chin of a user to prevent the user's chin and an inner surface of the mask from coming in contact with each other. The guide includes a first guide disposed on the inner surface of the mask. The guide includes a second guide configured to be positioned on the user's chin and configured to be moved in accordance with movement of the user's chin.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: An image processing method and apparatus is disclosed, where the image processing method includes receiving an image including frames captured over a time period in an illumination environment including alternating current (AC) light, estimating a specular chromaticity and a diffuse chromaticity of the image based on the frames, determining a weight of each of the specular chromaticity and the diffuse chromaticity based on a frame of the frames, and correcting the image based on the specular chromaticity, the diffuse chromaticity, the weight of the specular chromaticity, and the weight of the diffuse chromaticity.

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Abstract: An image processing method and apparatus is disclosed, where the image processing method includes receiving an image including frames captured over a time period in an illumination environment including alternating current (AC) light, estimating a specular chromaticity and a diffuse chromaticity of the image based on the frames, determining a weight of each of the specular chromaticity and the diffuse chromaticity based on a frame of the frames, and correcting the image based on the specular chromaticity, the diffuse chromaticity, the weight of the specular chromaticity, and the weight of the diffuse chromaticity.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Abstract: A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: A method is provided for managing data in an electronic device, the method including: detecting a request for tagging a data record; selecting a portion of the data record in response to the request; identifying a content item based on the selected portion of the data record; and associating the content item with the data record.

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Abstract: A semiconductor chip includes a substrate. An electrode pad is disposed on the substrate. The electrode pad includes a low-k material layer. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

Abstract: A 4 wheel drive vehicle removes sense of shift difference through an acceleration shift control mode, and the acceleration shift control mode transfers an independent other drive shaft input torque to a drive shaft not connected to a transmission with respect to a transmission input torque transferred to a drive shaft connected with the transmission, so that a vehicle acceleration in an actual shift section connecting between a fore-section and post-section of the shift can be maintained to be equal to the vehicle acceleration of the fore-section and post-section of the, thereby overcoming the transfer torque change, which is not overcome in a conventional slip control method, speed control method and time control method, when transferring a torque to the drive wheels in the actual shift section and realizing the shift quality without the sense of shift difference.

Abstract: A 4 wheel drive vehicle removes sense of shift difference through an acceleration shift control mode, and the acceleration shift control mode transfers an independent other drive shaft input torque to a drive shaft not connected to a transmission with respect to a transmission input torque transferred to a drive shaft connected with the transmission, so that a vehicle acceleration in an actual shift section connecting between a fore-section and post-section of the shift can be maintained to be equal to the vehicle acceleration of the fore-section and post-section of the, thereby overcoming the transfer torque change, which is not overcome in a conventional slip control method, speed control method and time control method, when transferring a torque to the drive wheels in the actual shift section and realizing the shift quality without the sense of shift difference.

Abstract: A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.