Patents by Inventor Chao-An Su

Chao-An Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11154949
    Abstract: An apparatus, system and method for micro welding, wherein insulated object, such as a wire, that includes a metallic conductor that is at least partially covered by one or more layers of insulation, is positioned across a termination point. A laser beam may be applied to an area of the insulated object overlapping the termination point, wherein the applied laser beam is configured to substantially simultaneously (i) ablate the one or more layers of insulation in a first region of the area, (ii) weld the metallic conductor to the termination point in a second region of the area, and (iii) detach a portion of the object from the termination point in a third region of the area.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 26, 2021
    Assignee: JABIL INC.
    Inventors: William Douglas Sterling, Chao Su, Gongen Gu
  • Patent number: 11017852
    Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Patent number: 11011224
    Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10956059
    Abstract: Methods, apparatus, and processor-readable storage media for classification of storage systems and users thereof using machine learning techniques are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; classifying one or more of the storage systems by applying a first set of machine learning techniques to the processed input data; classifying one or more respective users of the classified storage systems by applying a second set of machine learning techniques to the processed input data associated with the classified storage systems; and outputting, via one or more user interfaces, at least a portion of the storage system classifications and at least a portion of the user classifications to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Bina K. Thakkar, Roopa A. Luktuke, Aditya Krishnan, Chao Su, Deepak Gowda
  • Publication number: 20210034259
    Abstract: Methods, apparatus, and processor-readable storage media for classification of storage systems and users thereof using machine learning techniques are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; classifying one or more of the storage systems by applying a first set of machine learning techniques to the processed input data; classifying one or more respective users of the classified storage systems by applying a second set of machine learning techniques to the processed input data associated with the classified storage systems; and outputting, via one or more user interfaces, at least a portion of the storage system classifications and at least a portion of the user classifications to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Bina K. Thakkar, Roopa A. Luktuke, Aditya Krishnan, Chao Su, Deepak Gowda
  • Publication number: 20210034991
    Abstract: Methods, apparatus, and processor-readable storage media for implementing a machine learning-based recommendation engine for storage system usage within an enterprise are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; determining association rules applicable to the multiple storage systems by applying machine learning techniques to the processed input data; generating configuration-related recommendations applicable to one or more of the storage systems by applying content filtering techniques to the determined association rules; and outputting, via user interfaces, the configuration-related recommendations to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Bina K. Thakkar, Roopa A. Luktuke, Chao Su, Aditya Krishnan, Deepak Gowda
  • Publication number: 20210027316
    Abstract: Methods, apparatus, and processor-readable storage media for determining user retention values using machine learning and heuristic techniques are provided herein. An example computer-implemented method includes processing multiple forms of input data pertaining to interactions between a user and an enterprise; generating one or more user sentiment values from the processed input data by applying machine learning techniques to the processed input data; determining a user-specific estimate for the enterprise retaining the user, wherein determining the user-specific estimate comprises combining the one or more sentiment values with one or more storage system heuristics-based values derived from enterprise-related data; and outputting the user-specific estimate to at least one entity within the enterprise for use in connection with user-support actions.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 28, 2021
    Inventors: Bina K. Thakkar, Chao Su, Roopa A. Luktuke, Aditya Krishnan, Deepak Gowda
  • Publication number: 20210005524
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.
    Type: Application
    Filed: February 18, 2020
    Publication date: January 7, 2021
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Patent number: 10872406
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20200251395
    Abstract: An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulating layer encapsulates the electronic component and the conductive elements. The encapsulating layer is formed with recessed portions corresponding in position to the conductive elements. A gap is formed between the conductive elements and the recessed portions.
    Type: Application
    Filed: July 2, 2019
    Publication date: August 6, 2020
    Inventors: Chih-Chiang He, Yu-Wei Yeh, Chia-Yang Chen, Chih-Yi Liao, Chih-Hsien Chiu, Chang-Chao Su
  • Publication number: 20200105344
    Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi TU, Chu-Jie HUANG, Sheng-Hung SHIH, Nai-Chao SU, Wen-Ting CHU
  • Publication number: 20200105343
    Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi TU, Chu-Jie HUANG, Sheng-Hung SHIH, Nai-Chao SU, Wen-Ting CHU
  • Patent number: 10497436
    Abstract: A memory device includes a bottom electrode, a resistance switching layer and a top electrode. The bottom electrode is over a metallization layer embedded in an inter-metal dielectric layer. The bottom electrode has a top surface and a sidewall that extends at an obtuse angle relative to the top surface. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Publication number: 20190318471
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: August 29, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20190164602
    Abstract: A memory device includes a bottom electrode, a resistance switching layer and a top electrode. The bottom electrode is over a metallization layer embedded in an inter-metal dielectric layer. The bottom electrode has a top surface and a sidewall that extends at an obtuse angle relative to the top surface. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi TU, Chu-Jie HUANG, Sheng-Hung SHIH, Nai-Chao SU, Wen-Ting CHU
  • Publication number: 20190039180
    Abstract: An apparatus, system and method for micro welding, wherein insulated object, such as a wire, that includes a metallic conductor that is at least partially covered by one or more layers of insulation, is positioned across a termination point. A laser beam may be applied to an area of the insulated object overlapping the termination point, wherein the applied laser beam is configured to substantially simultaneously (i) ablate the one or more layers of insulation in a first region of the area, (ii) weld the metallic conductor to the termination point in a second region of the area, and (iii) detach a portion of the object from the termination point in a third region of the area.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 7, 2019
    Applicant: Jabil Circuit Inc.
    Inventors: William Douglas Sterling, Chao Su, Gongen Gu
  • Patent number: 10099315
    Abstract: An apparatus, system and method for micro welding, wherein insulated object, such as a wire, that includes a metallic conductor that is at least partially covered by one or more layers of insulation, is positioned across a termination point. A laser beam may be applied to an area of the insulated object overlapping the termination point, wherein the applied laser beam is configured to substantially simultaneously (i) ablate the one or more layers of insulation in a first region of the area, (ii) weld the metallic conductor to the termination point in a second region of the area, and (iii) detach a portion of the object from the termination point in a third region of the area.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: October 16, 2018
    Assignee: Jabil Inc.
    Inventors: William Douglas Sterling, Chao Su, Gongen Gu
  • Patent number: 9947678
    Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Hsieh, Chi-Wei Ho, Kao-Chao Lin, Josh Lin, Nai-Chao Su, Shih-Jung Tu, Po-Kai Hsu, Shih-Ching Lee, Chen-Ming Huang
  • Patent number: 9525024
    Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Su, Huang-Ming Chen, Chun-Feng Nieh, Pei-Chao Su