Patents by Inventor CHAO AN

CHAO AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090035898
    Abstract: A method of fabricating a layer with a tiny structure and a thin film transistor comprising the same is disclosed. The method of fabricating the layer with a tiny structure comprises providing a substrate, coating a coating composition on the substrate to form a coating layer, wherein the coating composition comprises nano conductive particles or nano semiconductor particles having functional groups bonded on a surface thereof uniformly dispersed in a solvent, and irradiating the coating layer by an additional energy to break the functional groups, resulting in aggregation of nano conductive particles or nano semiconductor particles to form a tiny structure.
    Type: Application
    Filed: October 18, 2007
    Publication date: February 5, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Chao-An Jong
  • Publication number: 20090015297
    Abstract: A source driver includes four output switches, two resistors, and a charge-sharing switch. The first output switch and the first resistor are coupled in series to a first output channel of the source driver. The second output switch and the second resistor are coupled in series to a second output channel of the source driver. The third output switch is coupled in parallel to the first output switch. The fourth output switch is coupled in parallel to the second output switch. The charge-sharing switch is coupled between the first resistor and the second resistor. The third output switch and the fourth output switch are controlled to adjust the resistance of the output current path of the source driver.
    Type: Application
    Filed: October 2, 2007
    Publication date: January 15, 2009
    Inventors: Chao-An Chen, Kuang-Feng Sung
  • Publication number: 20080308782
    Abstract: A semiconductor structure includes a transistor over a substrate, the transistor comprising a gate and a contact region, which is adjacent to the gate and within the substrate. A first dielectric layer is over the contact region. A contact structure is within the first dielectric layer and over the contact region. A first electrode and a second electrode are within the first dielectric layer, wherein at least one of the first electrode and the second electrode is over the contact structure. The first electrode and second electrodes may be laterally or vertically separated. A phase change structure is disposed between the first electrode and the second electrode. The phase change structure includes at least one spacer within the first dielectric layer and a phase change material (PCM) layer over the spacer.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shau-Lin Shue, Chao-An Jong
  • Publication number: 20080299700
    Abstract: A method of fabricating photodiode includes: a substrate comprising a well is provided, next, a first doping region is formed in the well, following that a conductive layer is formed on the surface of the first doping region by an epitaxial growth process, meanwhile, the conductive layer is in-situ doped to form a second doping region in the conductive layer. The method for fabricating the photodiode in the present invention can prevent the lattice structure from being damaged during the high dozes implantation process. Therefore, the dark current can be reduced and the sensitivity of the photodiode will be increased.
    Type: Application
    Filed: May 28, 2007
    Publication date: December 4, 2008
    Inventors: Bang-Chiang Lan, Tzung-I Su, Chien-Nan Kuo, Chao-An Su, Heng-Ching Lin, Shih-Wei Li, Wei-Chin Hung
  • Publication number: 20080290467
    Abstract: A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shau-Lin Shue, Chao-An Jong
  • Publication number: 20080029848
    Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.
    Type: Application
    Filed: September 12, 2006
    Publication date: February 7, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Zing Way Pei, Chao An Chung
  • Publication number: 20070243152
    Abstract: The present invention discloses a formula for fabricating skin treatment product, wherein the formula comprises at least one pectin enzyme and at least one cellulose enzyme. The formula is used to mix with an organic mixture to fabricate the desired skin treatment product, and the organic mixture comprises extract or artifact of nature product. Additionally, this invention also discloses a method for fabricating skin treatment product by use of the above-mentioned formula.
    Type: Application
    Filed: April 14, 2006
    Publication date: October 18, 2007
    Inventors: Chien-Chang Wang, Chao-An Chen
  • Publication number: 20060213122
    Abstract: A plant cultivation container includes a waste tire rubber, and a saturated resin mixed with the waste tire rubber. Thus, the waste tire rubber has a plurality of concave and convex surfaces arranged in a staggered manner and a plurality of gaps located between the concave and convex surfaces so that the plant can climb along the waste tire rubber, thereby facilitating cultivation of the plant. In addition, the plant cultivation container reuses the waste tire rubber to provide a recycling effect, thereby preventing the waste tire rubber from causing an environmental pollution so as to protect the ambient environment.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 28, 2006
    Inventor: Chao-An Chiu
  • Patent number: 6792378
    Abstract: A method for testing I/O ports of a computer motherboard under test. A non-volatile memory on the computer motherboard under test is provided with a test code for initializing the computer motherboard and testing its I/O ports, in which the test code includes a plurality of test routines corresponding to the I/O ports to be tested. Upon power-up or reboot, the computer motherboard under test is booted from the test code in the non-volatile memory. One of the I/O ports is selected from an interactive display menu, and then a CPU on the computer motherboard under test executes the corresponding test routine for the selected I/O port to test it. If there is an abnormal signal pin in the selected I/O port, a failure message is displayed to indicate which signal pin of the selected I/O port is not operating correctly. Otherwise, a pass message is displayed.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 14, 2004
    Assignee: Via Technologies, Inc.
    Inventors: Zhiguo Chen, Chih-Wei Huang, Chao-An Chen
  • Publication number: 20040102916
    Abstract: A method for testing I/O ports of a computer motherboard under test. A non-volatile memory on the computer motherboard under test is provided with a test code for initializing the computer motherboard and testing its I/O ports, in which the test code includes a plurality of test routines corresponding to the I/O ports to be tested. Upon power-up or reboot, the computer motherboard under test is booted from the test code in the non-volatile memory. One of the I/O ports is selected from an interactive display menu, and then a CPU on the computer motherboard under test executes the corresponding test routine for the selected I/O port to test it. If there is an abnormal signal pin in the selected I/O port, a failure message is displayed to indicate which signal pin of the selected I/O port is not operating correctly. Otherwise, a pass message is displayed.
    Type: Application
    Filed: November 21, 2002
    Publication date: May 27, 2004
    Inventors: Zhiguo Chen, Chih-Wei Huang, Chao-An Chen
  • Patent number: 6719506
    Abstract: Disclosed herein is a gantry type hybrid parallel linkage five-axis machine tool composed of a machine framework a parallel spatial linkage mechanism, a feeding shaft mechanism, and a controller unit. The parallel spatial linkage mechanism is formed of three straight feeding molding dies rotatably hinged together with a base so that enabling this rotatable base to perform uni-dimensional linear motion and two-dimensional swiveling. Besides by controlling the operation of the feeding shaft mechanism with the controller unit, the parallel spatial linkage mechanism fixed to the machine framework is able to perform two-dimensional planar motion so as to operate the machine tools more accurately and efficiently in refining work.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: April 13, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Tsann-Huei Chang, Kuan-Wen Chen, Chao-An Kang
  • Publication number: 20030077139
    Abstract: Disclosed herein is a gantry type hybrid parallel linkage five-axis machine tool composed of a machine framework a parallel spatial linkage mechanism, a feeding shaft mechanism, and a controller unit. The parallel spatial linkage mechanism is formed of three straight feeding molding dies rotatably hinged together with a base so that enabling this rotatable base to perform uni-dimensional linear motion and two-dimensional swiveling. Besides by controlling the operation of the feeding shaft mechanism with the controller unit, the parallel spatial linkage mechanism fixed to the machine framework is able to perform two-dimensional planar motion so as to operate the machine tools more accurately and efficiently in refining work.
    Type: Application
    Filed: December 11, 2001
    Publication date: April 24, 2003
    Inventors: Tsann-Huei Chang, Kuan-Wen Chen, Chao-An Kang