Patents by Inventor Chao-Cheng Chen

Chao-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to reduce etch variation using ion implantation
    Patent number: 10854729
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Metal gate electrode of a semiconductor device
    Patent number: 10854742
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Gate Structure with Desired Profile for Semiconductor Devices
    Publication number: 20200373401
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Method of Forming an Integrated Circuit
    Publication number: 20200312663
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 1, 2020
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yi-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Methods for removing particles from etching chamber
    Patent number: 10790124
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • Source/drain recess in a semiconductor device
    Patent number: 10784375
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • FinFET Device
    Publication number: 20200279945
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chen, Chao-Cheng Chen
  • Gate structure with desired profile for semiconductor devices
    Patent number: 10749007
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ricky Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Method for mandrel and spacer patterning
    Patent number: 10748768
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • CELLULOSE COMPOSITION
    Publication number: 20200247978
    Abstract: Provided is a cellulose composition, including a plurality of biocelluloses, wherein a diameter of the biocelluloses ranges from 20 to 30 nanometer, and a length of the biocelluloses ranges from 2000 to 3000 nanometer. The biocelluloses have good biocompatibility and can effectively enhance the efficiency of absorption and transmission of substances.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Inventors: Chao-Cheng Chen, Chi-Hsiang Lu, Jun-Wei Hong, Shang-Ru Lin
  • CULTIVATING MATERIAL COMPOSITION
    Publication number: 20200207676
    Abstract: Provided is a cultivating material composition including a cultivating substrate and a bio-cellulose film, wherein the bio-cellulose film is in contact with the cultivating substrate, such that highly increased yield and quality of crops, a shorter harvest period, less water and nutrient sources, and low cost can be achieved.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 2, 2020
    Inventors: Chao-Cheng Chen, Chi-Hsiang Lu
  • GATE STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD OF MAKING
    Publication number: 20200168721
    Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
  • Method of forming an integrated circuit using a patterned mask layer
    Patent number: 10665457
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Controlling profiles of replacement gates
    Patent number: 10658491
    Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Ming-Ching Chang, Chan-Lon Yang, Chao-Cheng Chen, Syun-Ming Jang
  • FinFET device
    Patent number: 10658509
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20200098919
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
  • Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks Using an Etch Barrier
    Publication number: 20200075588
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks Using an Etch Barrier
    Publication number: 20200075586
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Methods for Forming Fin Field-Effect Transistors
    Publication number: 20200043797
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Application
    Filed: September 30, 2019
    Publication date: February 6, 2020
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Gate structure of a semiconductor device
    Patent number: 10553699
    Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming Zhu, Hui-Wen Lin, Harry Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz