Patents by Inventor Chao-Cheng Chen

Chao-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming an integrated circuit using a patterned mask layer
    Patent number: 9934971
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Methods for removing particles from etching chamber
    Patent number: 9934945
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • FinFET Device
    Publication number: 20180090607
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Composite dummy gate with conformal polysilicon layer for FinFET device
    Patent number: 9923079
    Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Ryan Chia-Jen Chen, Ming-Ching Chang, Tzu-Yen Hsieh
  • METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE
    Publication number: 20180047585
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 15, 2018
    Inventors: Tzu-Yen HSIEH, Ming-Ching CHANG, Chia-Wei CHANG, Chao-Cheng CHEN, Chun-Hung LEE, Dai-Lin WU
  • Simultaneous formation of source/drain openings with different profiles
    Patent number: 9870954
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Semiconductor strips with undercuts and methods for forming the same
    Patent number: 9865708
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • FinFET device
    Patent number: 9825173
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Plasma generation and pulsed plasma etching
    Patent number: 9793127
    Abstract: One or more plasma etching techniques are provided. Selective plasma etching is achieved by introducing a gas into a chamber containing a photoresist over a substrate, establishing a bias at a frequency to convert the gas to a plasma at the frequency, and using the plasma to etch the photoresist. The frequency controls an electron density of the plasma and by maintaining a low electron density causes free radicals of the plasma to chemically etch the photoresist, rather than physically etching using ion bombardment. A mechanism is thus provided for chemically etching a photoresist under what are typically physical etching conditions.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu Chao Lin, Chao-Cheng Chen
  • Radiolabeled active targeting pharmaceutical composition and the use thereof
    Patent number: 9789214
    Abstract: The present invention is related to a radiolabeled active targeting pharmaceutical composition, including: a bioconjugate and a radionuclide, wherein the bioconjugate includes a biomolecule and a metal nanoparticle, wherein the biomolecule has an affinity for receptors on the surface of a cell membrane and is selected from the group consisting of a peptide and a protein. The present invention further provides a method for evaluating a thermal adjuvant therapy for tumors and a kit thereof. The above-mentioned pharmaceutical composition is applied to evaluate a tumor accumulation time, so as to establish the optimal policy for a radiofrequency- or laser-induced thermal adjuvant therapy for tumors.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: October 17, 2017
    Assignees: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, NATIONAL YANG-MING UNIVERSITY
    Inventors: Hsin-Ell Wang, Chien-Chung Hsia, Mao-Chi Weng, Kun-Liang Lin, Hao-Wen Kao, Chao-Cheng Chen, Kwan-Hwa Chi, Der-Chi Tien, Wuu-Jyh Lin
  • Method of fabricating a semiconductor structure
    Patent number: 9779963
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
  • Method and structure for metal gates
    Patent number: 9761684
    Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a gate dielectric layer over the substrate, a barrier layer over the gate dielectric layer, an oxide layer over the barrier layer, and a work function metal layer over the oxide layer.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ju-Li Huang, Chao-Cheng Chen, Calvin Chiang, Ming-Chia Tai, Ming-Hsi Yeh
  • Method of Forming an Integrated Circuit
    Publication number: 20170236712
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Methods for Forming Fin Field-Effect Transistors
    Publication number: 20170229348
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • METHOD FOR MANDREL AND SPACER PATTERNING
    Publication number: 20170194147
    Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.
    Type: Application
    Filed: April 12, 2016
    Publication date: July 6, 2017
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • METHOD OF FORMING GATE STRUCTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20170186853
    Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
  • Method of fabricating a semiconductor device including a plurality of isolation features
    Patent number: 9685344
    Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu Chao Lin, Chih-Tang Peng, Shun-Hui Yang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Iterative self-aligned patterning
    Patent number: 9685332
    Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Fang Chen, Huan-Just Lin, Chun-Hung Lee, Chao-Cheng Chen
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    Publication number: 20170170308
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes: providing a workpiece having a recess and a dielectric layer lining the recess; forming a conductive structure within the recess, wherein the conductive structure partially fills the recess; and recessing the dielectric layer, wherein, after the recessing, a top surface of the recessed dielectric layer is disposed within the recess.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 15, 2017
    Inventors: Yu Chao Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Method of forming an integrated circuit using a patterned mask layer
    Patent number: 9640398
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen