Patents by Inventor Chao-Ching Hsieh

Chao-Ching Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080132023
    Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Tsai-Fu Hsiao, Yu-Lan Chang, Tsung-Yu Hung, Chun-Chieh Chang
  • Publication number: 20080132063
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal alloy layer. A thermal process is performed so that the refractory metal alloy layer reacts with silicon of the silicon-containing conductive layer to form a refractory metal alloy salicide layer. Afterwards, an etch process with an etch solution is performed to removes the cap layer and the refractory metal alloy layer which has not been reacted and to form a protection layer on the refractory metal alloy salicide layer.
    Type: Application
    Filed: January 21, 2008
    Publication date: June 5, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Publication number: 20080073727
    Abstract: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Application
    Filed: July 27, 2007
    Publication date: March 27, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Publication number: 20080076213
    Abstract: A method of fabricating semiconductor device is provided. A transistor is formed on a substrate, and a metal suicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Inventors: Chao-Ching Hsieh, Chun-Chieh Chang, Tzung-Yu Hung
  • Publication number: 20080067684
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Application
    Filed: November 23, 2007
    Publication date: March 20, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Patent number: 7344978
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: March 18, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Publication number: 20080038887
    Abstract: A method of making a transistor device having silicided source/drain is provided. A gate electrode is formed on a substrate with a gate dielectric layer therebetween. A spacer is formed on sidewalls of the gate electrode. A source/drain is implanted into the substrate. A pre-amorphization implant (PAI) is performed to form an amorphized layer on the source/drain. A post-PAI annealing process is performed to repair defects formed during the PAI process. A metal silicide layer is then formed from the amorphized layer.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 14, 2008
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Wei Chen, Tzung-Yu Hung, Chun-Chieh Chang
  • Publication number: 20080020587
    Abstract: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is performed on the silicon substrate in order to strip the remnant metal.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Inventors: Chun-Chieh Chang, Tzung-Yu Hung, Chao-Ching Hsieh, Yi-Wei Chen, Yu-Lan Chang
  • Publication number: 20080009134
    Abstract: A method for fabricating a metal silicide is described. First, a silicon material layer is provided. An alloy layer is formed on the silicon material layer, and the alloy layer is made from a first metal and a second metal, wherein, the first metal is a refractory metal, and the second metal is selected from a group consisting of Pt, Pd, Mo, Ru, and Ta. A first rapid thermal process (RTP) is performed at a first temperature. A first cleaning process is performed by using a cleaning solution. A second RTP is performed at a second temperature, wherein the second temperature is higher than the first temperature. A second cleaning process is performed by using a cleaning solution including a hydrochloric acid.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 10, 2008
    Inventors: Tsung-Yu Hung, Chun-Chieh Chang, Chao-Ching Hsieh, Yi-Wei Chen, Yu-Lan Chang, Chien-Chung Huang
  • Publication number: 20070167009
    Abstract: A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
    Type: Application
    Filed: March 13, 2007
    Publication date: July 19, 2007
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Yi-Yiing Chiang, Tzung-Yu Hung, Yu-Lan Chang, Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen
  • Patent number: 7229920
    Abstract: A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a titanium silicide layer, is formed on the exposed substrate. After that, the hard mask layer is removed and a second metal silicide layer is formed over the gate, wherein a material of the second metal silicide layer is selected from a group consisting of nickel silicide, platinum silicide, palladium silicide and nickel alloy. Since different metal silicide layers are formed on the substrate and the gate, the problem of having a high resistance in lines with a narrow line width and the problem of nickel silicide forming spikes and pipelines in the source region and the drain region are improved.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: June 12, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Wei Chen, Tzung-Yu Hung, Yi-Yiing Chiang, Chao-Ching Hsieh, Yu-Lan Chang
  • Publication number: 20070087573
    Abstract: A pre-treatment method for physical vapor deposition of a metal layer is provided. A substrate is first provided and then a dry cleaning process is performed to the substrate using a chemical etching process, in which the chemical etching process causes a reaction to the oxide. Thereafter, an annealing process is performed, followed by a cooling process. Due to the treatment prior to depositing of the metal layer, subsequent metal layers from ill effects are prevented.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Yi-Yiing Chiang, Chao-Ching Hsieh, Tzung-Yu Hung, Yu-Lan Chang, Chien-Chung Huang, Yi-Wei Chen
  • Publication number: 20070082494
    Abstract: A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system of the first tool system is broken. The substrate is transferred from the first tool system into a second tool system. A metal silicide layer is formed over the substrate in the second tool system.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 12, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Yi-Yiing Chiang, Yu-Lan Chang, Tzung-Yu Hung, Chao-Ching Hsieh
  • Publication number: 20070059878
    Abstract: A salicide process includes providing a substrate, in which the surface of the substrate contains at least a silicon layer; performing a degas process on the substrate; performing a cooling process on the substrate; depositing a metal layer over the surface of the substrate, in which the surface of the metal layer and the surface of the silicon layer are in contact with each other; and removing the unreacted metal layer.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung, Jia-Rung Li
  • Publication number: 20070054481
    Abstract: A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Yi-Yiing Chiang, Tzung-Yu Hung, Yu-Lan Chang, Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen
  • Publication number: 20070049017
    Abstract: A method of fabricating a plug for a hole in a dielectric layer is disclosed. The method includes a first deposition process to partially filling the hole with a conductive material. Later, an etching process is performed at the partially filled hole. In addition, a second deposition process is performed to partially fill the hole with the conductive material again. Finally, the above steps are repeated until the hole is completely filled. The first deposition process and the second deposition process are done using a CVD or a PVD process. In addition, the etching process is done using halogen-containing gas.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 1, 2007
    Inventor: Chao-Ching Hsieh
  • Publication number: 20070032077
    Abstract: A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed to remove the metallic layer outside the opening. One main feature of the present invention is the performance of at least a high temperature treatment after the metallic layer is formed. Due to the high temperature treatment, internal stress between different layers is released.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Tzung-Yu Hung, Chien-Chung Huang, Chao-Ching Hsieh, Chia-Lin Hsu
  • Publication number: 20070020925
    Abstract: A substrate having at least one silicon device is provided. A nickel platinum alloy layer is formed on the substrate. A rapid thermal process is performed to react the nickel platinum alloy layer with the silicon device to produce a nickel platinum silicide. A passivation layer is formed on the nickel platinum silicide followed by using a solution consisting of nitric acid and hydrochloric acid to remove unreacted portions of the nickel platinum alloy layer.
    Type: Application
    Filed: July 22, 2005
    Publication date: January 25, 2007
    Inventors: Chao-Ching Hsieh, Yi-Yiing Chiang, Tzung-Yu Hung, Yi-Wei Chen, Yu-Lan Chang
  • Publication number: 20060284263
    Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Yu-Lan Chang, Chao-Ching Hsieh, Yi-Yiing Chiang, Yi-Wei Chen, Tzung-Yu Hung
  • Publication number: 20060240666
    Abstract: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the silicide to break up lattice structure of the silicide, so that the problem of junction leakage induced by spiking and piping diffusion under high temperature during a subsequent second annealing process is avoided.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Chao-Ching Hsieh, Yi-Yiing Chiang, Chien-Chung Huang, Po-Chao Tsou, Kirk Hsu, Tony Lin, Le-Tien Jung