Abstract: This disclosure covers systems and methods that retrieve and transform a requested dataset into a data shape that a widget specifies for visualization. In certain embodiments, the disclosed systems and methods respond to data requests for widgets by retrieving datasets formatted according to different data models for different platforms. The systems and methods then transform the datasets into a data shape specified by the widgets. By transforming requested datasets to conform to data shapes specified by widgets, the disclosed systems and methods orchestrate the update of a widget (or multiple instances of a widget) with data that originally conformed to different data models and, in some cases, was formatted for different software applications.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: This disclosure covers systems and methods that retrieve and transform a requested dataset into a data shape that a widget specifies for visualization. In certain embodiments, the disclosed systems and methods respond to data requests for widgets by retrieving datasets formatted according to different data models for different platforms. The systems and methods then transform the datasets into a data shape specified by the widgets. By transforming requested datasets to conform to data shapes specified by widgets, the disclosed systems and methods orchestrate the update of a widget (or multiple instances of a widget) with data that originally conformed to different data models and, in some cases, was formatted for different software applications.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A network device includes a timing module, a traffic analysis module, a counting module, a mode switching module and at least one processor. The timing module sets a plurality of continual timing periods each including a plurality of timing periods. The traffic analysis module analyzes if the traffic transmitted by the network device in each of the timing periods in a continual timing period is less than a predetermined traffic threshold, and defining a first analysis result every time that the traffic transmitted through the network device in each of the timing periods in the continual timing period is less than the predetermined traffic threshold. The counting module counts an amount of the first analysis results, and determines if the counted amount is less than a predetermined threshold. The mode switching module switches the working mode of the network device according to the determination of the counting module.

Abstract: A network device includes a timing module, a traffic analysis module, a counting module, a mode switching module and at least one processor. The timing module sets a plurality of continual timing periods. Each of the continual timing periods includes a plurality of timing periods The traffic analysis module analyzes if the traffic transmitted by the network device in each of the timing periods in a continual timing period is less than a predetermined traffic threshold. The counting module counts an amount of the traffic transmitted through the network device is less than the predetermined traffic threshold in the continual timing period, and determines if the counted amount is less than a predetermined threshold. The mode switching module switches the working mode of the network device according to the determination of the counting module. The processor executes the timing module, the traffic analysis module, the counting module, and the mode switching module.

Abstract: A paste composition for forming an electrically conductive layer on a p-type silicon semiconductor substrate comprises aluminum powder, an organic vehicle and powder of at least one inorganic compound selected from a group consisting of an oxide-based inorganic compound and a non-oxide-based inorganic compound. The oxide-based inorganic compound has a thermal expansion coefficient smaller than the thermal expansion coefficient of aluminum and a melting temperature, a softening temperature and a decomposition temperature each higher than the melting point of aluminum. The non-oxide-based inorganic compound has a thermal expansion coefficient smaller than the thermal expansion coefficient of aluminum and at least one of a melting temperature, a softening temperature or a decomposition temperature higher than the melting point of aluminum.

Abstract: A network apparatus (10) for network address translation (NAT) configuration includes a web server (200), a wide area network (WAN) setting module (300), a dynamic host configuration protocol (DHCP) setting module (400), and an NAT setting module (500). The web server receives a WAN protocol message and an easy-mode enable message. The WAN setting module sets the WAN protocol message. The DHCP setting module sets DHCP predefined information according to the easy-mode enable message. The NAT setting module sets NAT predefined information according to the easy-mode enable message. The setting results of the WAN setting module, the DHCP setting module, and the NAT setting module are executed to complete the NAT configuration of the network apparatus. An NAT configuration method thereof is also provided.

Abstract: A network device with routing function (10) includes a receiving module (100) for receiving packets, a routing module (140), a parsing module (120), and a policy route setting module (130). Each of the packets has a source IP address therein. The routing module includes a route table including a plurality of destination IP addresses. The parsing module is used for parsing the packets to retrieve source IP addresses therein, and for determining whether one of the destination IP addresses matches the source IP addresses to determine whether new policy routes are needed. The policy route setting module is used for setting the new policy routes including destination addresses matching the source addresses of the packets, and saving the new policy routes in the route table.

Abstract: A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.

Abstract: A liquid crystal display device (100 or 200) includes a first substrate (110 or 210) and a second substrate (120 or 220) opposite to each other, a liquid crystal layer (130 or 230) sandwiched between the first and second substrates; a common electrode (140 or 240) formed on the first substrate, and the common electrode having a plurality of openings (180 or 280); and a plurality of gate lines (150 or 250) formed on the second substrate and positionally corresponding the openings respectively. Moreover, the gate lines can be arranged with the areas of the second substrate corresponding to the openings. The coupled capacitor delaying of signals of gate electrodes in the TFTs can be reduced. Accordingly, flickering can be reduced, and the display performance can be improved.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: An optical recording medium includes a substrate, a plurality of grooves, a plurality of lands and a plurality of land protrusions. The grooves are formed on the substrate, and the lands are formed between the grooves. The land protrusions are formed on the lands.

Abstract: A utility knife includes a housing having two plates secured together, to form a space between the plates, a knife blade has one end rotatably secured to the plates, to allow the knife blade to rotate out of the housing toward a working position or to rotate into the space of the housing toward a storing position. A latch is movably received in the plates and engageable into and out of a lock notch of the knife blade, to selectively lock the knife blade to the plates at the working position. A spring member may bias the latch into the notch of the knife blade, and to selectively lock the knife blade to the housing at the working position.

Abstract: An in-plane switching (IPS) liquid crystal display device (100) includes pixel units each having a storage capacitor. The storage capacitor is formed by a common electrode (112), a drain electrode (103), and a counter electrode (110). The common electrode is electrically coupled with the counter electrode. The counter electrode substantially covers the drain electrode, for shielding unexpected coupling effects on the drain electrode due to data signals on a data line (101) driving other pixels of the liquid crystal display device.

Abstract: A method for removing at least one of chromate and other oxy-metal ions from liquid solutions includes contacting the liquid solution with solid barium compounds as adsorbents so that the at least one of chromate and other oxy-metal ions in liquid solution are subject to an exchange reaction with the anion of solid barium compounds to produce products including at least one of solid barium chromate and oxy-metal barium compounds and are removed from the liquid solution by a liquid-solid separation operation. A method for stabilizing at least one of chromate and other oxy-metal ions that are present in liquid or sludge wastes includes mixing the liquid or sludge wastes with barium compounds in solid form, so that the at least one of chromate and oxy-metal ions are immobilized in a solidified body after curing of the mixture.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.