Abstract: A device housing includes a substrate and a decorative article formed in the substrate. The substrate defines a cutout therein and the decorative article is received in the cutout and bonded with the substrate. The decorative article is a glass article which is formed in the cutout by molding softened glass material into the cutout. A method for making the device housing is also provided.

Abstract: A device housing includes a main body and a first decorative layer formed on the main body. The main body defines a planar region and at least a concave region connected with the planar region. The first decorative layer includes a first pattern and a second pattern. The first pattern is formed on the planar region. The second pattern is formed on the concave region. The first pattern and the second pattern are an integral structure. A method for making the device housing is also provided.

Abstract: A device housing includes a stainless steel substrate having a first metallic coating and a second metallic coating formed thereon and in that order. The stainless steel substrate has at least one recess defined in an outer surface. The first metallic coating and a second metallic coating have different colors. The first metallic coating is left exposed in the recesses but covered elsewhere by the second metallic coating to form a desired symbol, logo, or pattern on the device housing. A method for making the present device housing also is provided.

Abstract: A device housing for an electronic device is provided. The device housing includes a stainless steel substrate and at least one metal decorative member. The stainless steel substrate has at least one receiving recess defined in an outer surface and has a metallic coating formed on the outer surface. The at least one metal decorative member has a top surface. The top surface has a mirror finish. The at least one metal decorative member is received in the at least one receiving recess, with the top surface exposed out of the outer surface. The at least one metal decorative member forms a desired symbol, logo, or pattern on the device housing.

Abstract: A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.

Abstract: A device housing for an electronic device is provided. The device housing includes a metal main body and at least one metal decorative member. The metal main body has at least one receiving recess defined in an outer surface thereof. The at least one metal decorative member has a top surface. The top surface has a mirror finish. The at least one metal decorative member is received in the at least one receiving recess, with the top surface exposed out of the outer surface. The at least one metal decorative member forms a desired symbol, logo, or pattern on the device housing.

Abstract: A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.

Abstract: For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting circuit.

Abstract: A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to the level-processing unit and biased between the first voltage and the second voltage. While the first voltage is in an OFF state and the second voltage is switched on, the voltage-drop unit provides an initializing voltage for the level-processing unit according to the second voltage to shift the input signal to provide the output signal.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target readout bit line from multiple readout bit lines according to a selecting signal. The sense amplifier detects the voltage of the target readout bit line after the target memory cell is selected to be readout.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target readout bit line from multiple readout bit lines according to a selecting signal. The sense amplifier detects the voltage of the target readout bit line after the target memory cell is selected to be readout.

Abstract: Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages received by the pull-down circuit are reduced and thus transistors of thinner gates may be used, effectively improving switching speed of transistors in the pull-down circuit. As such, noise and jiggle of the output voltage are reduced.

Abstract: A pull-up device coupled between an input/output (I/O) pad and a core circuit and has a static pull-up circuit, an adjustment unit, and a control circuit. The static pull-up circuit is coupled to the core circuit and receives a supply voltage. The adjustment unit is coupled to the I/O pad and generates an adjustment signal according to an input voltage of the I/O pad. The control circuit is coupled to the adjustment unit and the static pull-up circuit and controls the static pull-up circuit according to the adjustment signal.

Abstract: For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting circuit.

Abstract: A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to the level-processing unit and biased between the first voltage and the second voltage. While the first voltage is in an OFF state and the second voltage is switched on, the voltage-drop unit provides an initializing voltage for the level-processing unit according to the second voltage to shift the input signal to provide the output signal.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target readout bit line from multiple readout bit lines according to a selecting signal. The sense amplifier detects the voltage of the target readout bit line after the target memory cell is selected to be readout.

Abstract: A pull-up device coupled between an input/output (I/O) pad and a core circuit and has a static pull-up circuit, an adjustment unit, and a control circuit. The static pull-up circuit is coupled to the core circuit and receives a supply voltage. The adjustment unit is coupled to the I/O pad and generates an adjustment signal according to an input voltage of the I/O pad. The control circuit is coupled to the adjustment unit and the static pull-up circuit and controls the static pull-up circuit according to the adjustment signal.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a target memory cell is read to the read bit line, wherein the target memory cell is one of the plurality of memory cells, and a sense amplifier, coupled to the read bit line, detecting the voltage of the read bit line after the stored bit of the target memory cell is read to the read bit line, and comparing the voltage of the read bit line with the logic high level to respectively generate a comparison result signal and an inverse comparison result signal to a first output node and a second output node.

Abstract: A multi-layer universal serial bus (USB) input/output (I/O) system comprising a chipset, at least one USB port, and an I/O port. The chipset controls data transmission. The I/O control chip is coupled between the system chipset and the USB port. The chipset controls data transmission of the USB port through the I/O control chip.

Abstract: A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit is to output detecting pulses in response to any input pulse. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse.