Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target readout bit line from multiple readout bit lines according to a selecting signal. The sense amplifier detects the voltage of the target readout bit line after the target memory cell is selected to be readout.

Abstract: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a target memory cell is read to the read bit line, wherein the target memory cell is one of the plurality of memory cells, and a sense amplifier, coupled to the read bit line, detecting the voltage of the read bit line after the stored bit of the target memory cell is read to the read bit line, and comparing the voltage of the read bit line with the logic high level to respectively generate a comparison result signal and an inverse comparison result signal to a first output node and a second output node.

Abstract: Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages received by the pull-down circuit are reduced and thus transistors of thinner gates may be used, effectively improving switching speed of transistors in the pull-down circuit. As such, noise and jiggle of the output voltage are reduced.

Abstract: A voltage regulator and regulating method thereof are provided for providing a stable output voltage. The voltage regulating circuit includes an operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein said negative input terminal is connected to a reference voltage; a current mirror having a reference terminal and a mirror terminal; and a first transistor having a gate connected to the output terminal of the operational amplifier, a source connected to the reference terminal of the current mirror, and a drain connected to the positive input terminal of the operational amplifier.

Abstract: An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger connects to a common output node of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected.

Abstract: An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit, an output inverter and a feedback path circuit. The charge and discharge path circuit connects to a common output node and generates a potential on its output terminal in accordance with a first grounding path on or not. The voltage hold circuit controls a voltage of the common output node in accordance with both a second grounding path on or not and the potential on the output terminal of the charge and discharge path circuit. The output inverter generates and next outputs an inverted voltage on its output terminal in accordance with the potential on the output terminal of the charge and discharge path circuit. The feedback path circuit connects to output terminals of the charge and discharge path circuit and the output inverter.

Abstract: A level shifter is provided, which is characterized by adding a PMOS transistor to each pair of NMOS and PMOS transistors in the conventional level shifter. Wherein, a first source/drain terminal and gate terminal of the added PMOS transistor are coupled to a second source/drain terminal and a gate terminal of the NMOS transistor, respectively. A second source/drain terminal of the added PMOS transistor is coupled to a first source/drain terminal of the PMOS transistor. When the NMOS transistor is turned on, the added PMOS transistor is turned off. Accordingly, the operation of the NMOS and PMOS transistors do not affect each other. As a result, the fighting effect can be avoided.

Abstract: A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit is to output detecting pulses in response to any input pulse. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse.

Abstract: An output device for static random access memory (SRAM) is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger is connected to a common output node for a plurality of memory cells. The precharger has a precharge node and at least one transmitting gate coupled to the common output node and the precharge node. When one of the memory cells is to be read, the precharge node is precharged to a high potential. A gate of the transmitting gate is connected to a high potential so that a potential of the common output node is charged only to a potential of (Vdd-VT) when precharging. Thus, the common output node's potential can be pulled more faster down to a low potential, thereby increasing read speed on memory cells.

Abstract: An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger connects to a common output node of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected.

Abstract: An inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.

Abstract: An inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.