Patents by Inventor Chao-Wen Shih

Chao-Wen Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and manufacturing method thereof
    Patent number: 10319692
    Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Hao-Yi Tsai, Mirng-Ji Lii
  • Structure and formation method of chip package with antenna element
    Patent number: 10312203
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Ping Chiang, Nien-Fang Wu, Min-Chien Hsiao, Yi-Che Chiang, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Manufacturing method of semiconductor package
    Patent number: 10312209
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Wen Shih, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Shih-Wei Liang, Yen-Ping Wang
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190157224
    Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
    Type: Application
    Filed: January 21, 2019
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • PACKAGE STRUCTURES
    Publication number: 20190157206
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Package structure, electronic device and method of fabricating package structure
    Patent number: 10276920
    Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Chien Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10269904
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Tsung-Yuan Yu, Min-Chien Hsiao, Chao-Wen Shih
  • SEMICONDUCTOR PACKAGES AND MANUFACTURING MEHTODS THEREOF
    Publication number: 20190115271
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 18, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • PACKAGE STRUCTURE
    Publication number: 20190103652
    Abstract: A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.
    Type: Application
    Filed: January 25, 2018
    Publication date: April 4, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20190096828
    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
  • PACKAGE STRUCTURE, ELECTRONIC DEVICE AND METHOD OF FABRICATING PACKAGE STRUCTURE
    Publication number: 20190097304
    Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Chien Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • PACKAGE STRUCTURE AND METHOD OF FABRICATING PACKAGE STRUCTURE
    Publication number: 20190067220
    Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190027449
    Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Package structure and manufacturing method thereof
    Patent number: 10186492
    Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Semiconductor structure and method of manufacturing the same
    Patent number: 10183858
    Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Albert Wan, Yu-Sheng Hsieh, Chao-Wen Shih, Shou Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Sensor packages and manufacturing mehtods thereof
    Patent number: 10157807
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20180269139
    Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.
    Type: Application
    Filed: June 30, 2017
    Publication date: September 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Shou-Zen Chang, Yi-Che Chiang
  • Integrated Devices in Semiconductor Packages and Methods of Forming Same
    Publication number: 20180247905
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Application
    Filed: October 5, 2017
    Publication date: August 30, 2018
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
    Publication number: 20180233472
    Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: CHAO-WEN SHIH, KAI-CHIANG WU, CHING-FENG YANG, MING-KAI LIU, SHIH-WEI LIANG, YEN-PING WANG
  • STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH ANTENNA ELEMENT
    Publication number: 20180166405
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Application
    Filed: June 16, 2017
    Publication date: June 14, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Yung-Ping CHIANG, Nien-Fang WU, Min-Chien HSIAO, Yi-Che CHIANG, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU