Patents by Inventor Chao Yang

Chao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230389434
    Abstract: A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Oscar van der Straten, Koichi Motoyama, Scott A. DeVries, Chih-Chao Yang
  • Patent number: 11827194
    Abstract: Disclosed is a multi-mode electro-hydraulic brake boosting system and a control method thereof. When the boosting system fails, an emergency mechanical braking mode is achieved through structural redundancy, in a normal boosting mode, the system has a general braking mode and an emergency braking mode according to the strength requirements of a brake, and a general brake boosting mode and an emergency active pressurizing mode are controlled, respectively. Accurate boosting can be provided in the general braking process so that the pressure of a brake master cylinder can accurately follow target pressure, pressure buildup of the brake master cylinder can be completed more quickly in the emergency braking process, braking force is output to the maximum extent, the system response time of an emergency braking working condition is shortened, the braking capacity is improved, and traffic accidents are avoided.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 28, 2023
    Assignee: Beijing Institute of Technology
    Inventors: Weida Wang, Yanjie Wu, Changle Xiang, Liang Li, Jingang Liu, Zhongguo Zhang, Chao Yang
  • Patent number: 11830786
    Abstract: A flip-chip semiconductor package with improved heat dissipation capability and low package profile is provided. The package comprises a heat sink having a plurality of heat dissipation fins and a plurality of heat dissipation leads. The heat dissipation leads are connected to a plurality of thermally conductive vias of a substrate so as to provide thermal conductivity path from the heatsink to the substrate as well as support the heatsink to relieve compressive stress applied to a semiconductor die by the heatsink. The package further comprises an encapsulation layer configured to cover the heat dissipation leads of the heat sink and expose the heat dissipation fins of the heat sink.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 28, 2023
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Jingyu Shen, Qiyue Zhao, Chunhua Zhou, Chao Yang, Weigang Yao, Baoli Wei
  • Publication number: 20230369479
    Abstract: The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.
    Type: Application
    Filed: May 25, 2021
    Publication date: November 16, 2023
    Inventors: Qiyue ZHAO, Chunhua ZHOU, Maolin LI, Wuhao GAO, Chao YANG, Guanshen YANG, Shaopeng CHENG
  • Publication number: 20230371394
    Abstract: A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Oscar van der Straten, Koichi Motoyama, Kenneth Chun Kuen Cheng, Joseph F. Maniscalco, Chih-Chao Yang
  • Patent number: 11817389
    Abstract: A semiconductor device structure includes a memory element disposed within an interlayer dielectric (ILD) layer. A contact is disposed within the ILD in contact with the memory element and includes a first metal. A logic element is disposed within the ILD and comprises a second metal that is different than the first metal. A method of forming the semiconductor structure includes forming at least one memory element within an interlayer dielectric (ILD) layer. A contact that includes a first metal is formed in contact with the memory element. At least one logic element is formed in the ILD layer, where the logic element includes a second metal that is different than the first metal.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Chih-Chao Yang, Yann Mignot, Shanti Pancharatnam
  • Publication number: 20230363179
    Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Ashim DUTTA, Ekmini Anuja DE SILVA, Chih-Chao YANG
  • Publication number: 20230358529
    Abstract: The invention provides an optical pressure sensor. The light-emitting module emits a detection light, and the light-receiving module receives a reflected light reflected by an object. When the distance between the object and the light-receiving module changes due to external pressure, the intensity of reflected light changes. The control module compares the intensity difference of the signal to determines the pressing state.
    Type: Application
    Filed: June 14, 2022
    Publication date: November 9, 2023
    Inventors: WEI-TING LIN, SHENG-CHENG LEE, CHAO-YANG HSIAO
  • Publication number: 20230361158
    Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventors: HUIMEI ZHOU, Baozhen Li, Chih-Chao Yang, Ashim Dutta
  • Publication number: 20230359792
    Abstract: A method and system for high-speed transient thermal simulation of an electronic device and belongs to the technical field of high-speed transient thermal simulation of electronic devices. According to acquired parameter data of the electronic device, a dynamic weak balance relationship among heat generation amount, internal energy increment and heat dissipation amount of the electronic device is calculated to obtain a functional relationship between operating temperature and time of the electronic device; a trough temperature value of a transient temperature curve of electronic device in weak balance state is obtained by limit solving algorithm; an initial temperature is set in a manner of loading a fixed-temperature heat source, and simulating calculation is performed for a first preset number of cycles to obtain an initial temperature field; and a high-speed transient temperature change of the electronic device is obtained by the operation of a second preset number of pulse stress cycles.
    Type: Application
    Filed: August 18, 2022
    Publication date: November 9, 2023
    Applicant: SHANDONG UNIVERSITY
    Inventors: Jiayue YANG, Jian WANG, Zhiwei FU, Chao YANG, Dezhi MA
  • Patent number: 11807908
    Abstract: Provided is a group of peripheral blood gene markers for screening benign and malignant pulmonary micro-nodules, comprising: gene sequences characterized by micronodular lung carcinoma as shown in SEQ ID NOs. 1-6, wherein the gene sequences exhibit differential expression in the peripheral blood of micronodular lung carcinoma patients and non-micronodular lung carcinoma patients. In addition, also provided is the use of the above-mentioned gene markers in preparing a product for early screening micronodular lung carcinoma. The gene markers of the invention used for early screening micronodular lung carcinoma, have high sensitivity and strong specificity; besides, they take peripheral blood, which is the easiest to collect in clinic, as the test sample.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 7, 2023
    Assignee: Shanghai Biomedical Laboratory Co., Ltd.
    Inventors: Changming Cheng, Chao Yang, Ruiqin Ma, Yin Zhou
  • Patent number: 11804378
    Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Raghuveer R Patlolla, Donald F Canaperi, Cornelius Brown Peethala, Chih-Chao Yang, Mary Breton
  • Patent number: 11804636
    Abstract: One aspect of the present application provides an electrode assembly, including a first electrode plate, a second electrode plate, and a separator disposed therebetween. The first electrode plate and the second electrode plate are wound or stacked to form the electrode assembly. Wherein the electrode assembly further includes a first electrode tab disposed on the first electrode plate, and an insulating layer including a first portion disposed on the first electrode plate. And, no second electrode plate is disposed between the first portion and the first electrode tab. The present application also provides a battery. The present application intends to at least improve the safety performance of the battery.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 31, 2023
    Assignee: Dongguan Amperex Technology Limited
    Inventors: Yanan Zhang, Chao Yang, Wenwei Yin, Chunhua Bian
  • Publication number: 20230345841
    Abstract: Embodiments of present invention provide a method of forming electrode to a magnetic-tunnel junction device. The method includes providing a supporting structure; depositing a layer of conductive material on top of the supporting structure; performing a first etching of the layer of conductive material to form a connection layer; and performing a second etching of a remaining portion of the layer of conductive material to form a micro-stud, the micro-stud being directly above the connection layer. In one embodiment the supporting structure includes a via opening and the conductive material fills the via opening to form a via.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Inventors: Hsueh-Chung Chen, Koichi Motoyama, CHANRO PARK, Chih-Chao Yang
  • Patent number: 11797191
    Abstract: System and method for storage data in SSD may be provided. The method may include receiving data writing feature information sent by a file system during an initialization process. The method may include determining, based on the data writing feature information, a size of metadata storage space corresponding to the metadata. The method may further include determining, based on the size of metadata storage space, a target storage region for storing the metadata in the SSD.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 24, 2023
    Assignee: ZHEJIANG HUAYIXIN TECHNOLOGY CO., LTD.
    Inventor: Chao Yang
  • Patent number: 11797200
    Abstract: A provided a storage device configured to support a number of namespaces. The storage device includes a memory and a controller coupled to the memory. The controller includes a host interface layer and a flash translation layer configured to report to the host interface layer a first over-provisioning chunk from an over-provisioning pool and a first chunk separate from the over-provisioning pool. The controller is configured to receive a command at the host interface layer to utilize a portion of the memory for a first namespace from among the number of namespaces and the first namespace includes an unaligned chunk. The controller is configured to utilize the first over-provisioning chunk as the unaligned chunk of the first namespace. A number of over-provisioning chunks to be utilized as unaligned chunks is less than the number of namespaces.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiang Lian, Chao Yang
  • Publication number: 20230334239
    Abstract: A method includes receiving a request from a user device accessing a webpage, the request including a webpage uniform resource locator (URL) and a user device identifier. The method includes retrieving a list of events associated with the user device based on the device identifier. The method further includes retrieving sets of rules. Each set of rules indicates events and URLs that satisfy the set of rules. Each set of rules is associated with a template that includes link rendering data for rendering a link on the user device. The method includes identifying a set of rules that is satisfied by the received URL and events, transmitting link rendering data associated with the identified set of rules to the user device, and transmitting link routing data to the user device. The link routing data is configured to route the user device to an application state corresponding to the webpage.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Applicant: Branch Metrics, Inc.
    Inventors: Alexander Austin, William Lindemann, Cheng-chao Yang, Eric J. Glover, Dmitri Gaskin, Kan Yu, Sofus Macskassy
  • Publication number: 20230337474
    Abstract: A display device, a display panel, and a manufacturing method thereof are proposed. The display panel includes a substrate, a first insulation layer, a first electrode layer, a pixel definition layer, a light-emitting function layer and a second electrode.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Kuanta HUANG, Yuhao LEE, Dacheng ZHANG, Hui TONG, Xiaobin SHEN, Shipeng LI, Chao YANG, Dongsheng LI
  • Publication number: 20230337473
    Abstract: A display device, a display panel, and a manufacturing method thereof are proposed. The display panel includes a substrate, a first insulation layer, a first electrode layer, a pixel definition layer, a light-emitting function layer and a second electrode.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Kuanta HUANG, Yuhao LEE, Dacheng ZHANG, Hui TONG, Xiaobin SHEN, Shipeng LI, Chao YANG, Dongsheng LI
  • Patent number: D1003862
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 7, 2023
    Inventor: Chao Yang