Abstract: A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Abstract: An interconnect structure includes a diffusion barrier layer disposed on exterior surfaces of an opening in a dielectric layer. A top surface of the diffusion barrier layer is below a top surface of the opening. A liner layer is disposed on a bottom surface and sidewalls of the diffusion barrier layer. A spacer layer is disposed on the top surface of the diffusion barrier layer and the liner layer and exposed sidewalls of the opening. An interconnect metal is disposed on the liner layer and the spacer layer. A metal cap is disposed on the interconnect metal.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode. A semiconductor device including a MTJ stack, vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode, and an encapsulation layer surrounding vertical side surfaces of the MTJ stack, wherein the encapsulation layer does not surround the top electrode nor the bottom electrode. Forming a bottom electrode in a first inter-layer dielectric, forming a reference layer on the first inter-layer dielectric and on the bottom electrode, forming a tunnel barrier layer on the reference layer, forming a free layer on the tunnel barrier layer and patterning the reference layer, the tunnel barrier layer and the free layer into a magnetic tunnel function (MTJ) stack vertically aligned over the bottom electrode, while not patterning the bottom electrode nor the first inter-layer dielectric.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate electrode. The first nitride-based semiconductor layer includes at least two doped barrier regions defining an aperture between the doped barrier regions. The second nitride-based semiconductor layer is disposed over first nitride-based semiconductor layer. The third nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer and has a bandgap higher than a bandgap of the second nitride-based semiconductor layer. The passivation layer is disposed over the third nitride-based semiconductor layer, in which a vertical projection of the passivation layer on the first nitride-based semiconductor layer is spaced apart from the aperture. The gate insulator layer is disposed over the third nitride-based semiconductor layer.

Abstract: The present invention relates to a Si-containing high-strength and low-modulus medical titanium alloy, and an additive manufacturing method and use thereof. The additive manufacturing method comprises alloy ingredient design, powder preparation, model construction and substrate preheating, and additive manufacturing molding; wherein the Si-containing high-strength and low-modulus medical titanium alloy is designed in the ingredient proportion of Ti 60-70 at. %, Nb 16-24 at. %, Zr 4-14 at. %, Ta 1-8 at. %, Si 0.1-5 at. %.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A touch structure and a display panel are provided. The touch structure includes: first mesh electrodes extending in a first direction and second mesh electrodes extending in a second direction. The touch structure is absent in a window region. First mesh electrodes include at least one cross-window row separated by the window region, which includes a first cross-window row including: a first window mesh block adjacent to the window region and on a first side of the window region; a first conductive plate directly connected to mesh lines of the first window mesh block; and a first non-window mesh block on a side of the first window mesh block away from the window region; second mesh electrodes include at least one cross-window column including a first cross-window column which includes: a second window mesh block; a second conductive plate; and a second non-window mesh block.

Abstract: A robot joint, including: a housing; an output shaft, at least partially housed inside the housing and provided with a shaft portion and a flange portion at a first end of the shaft portion; a first bearing portion, housed in the housing and supporting a first position of the flange portion of the output shaft; a second bearing portion, housed in the housing and supporting a second position of the output shaft in an axial direction; and a motor, housed in the housing, where the second bearing portion is arranged between the motor and the first bearing portion along the axial direction of the output shaft. Further provided is a robot. By effectively supporting the output shaft at multiple points, the output shaft is enabled to more effectively and stably bear the moment or bending moment of a load, and the robot joint structure is enabled to be compact and lighter.

Abstract: A light-emitting device comprises a substrate comprising a top surface; a plurality of light-emitting units formed on the top surface of the substrate comprising a first light-emitting unit, a second light-emitting unit, and one or a plurality of third light-emitting units, wherein each of the plurality of light-emitting units comprises a first semiconductor layer, an active layer and a second semiconductor layer; an insulating layer comprising a first insulating layer opening and a second insulating layer opening formed on each of the plurality of light-emitting units; a first extension electrode covering the first light-emitting unit, wherein the first extension electrode covers the first insulating layer opening on the first light-emitting unit without covering the second insulating layer opening on the first light-emitting unit; a second extension electrode covering the second light-emitting unit, wherein the second extension electrode covers the second insulating layer opening on the second light-emittin

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

Abstract: Provided are a computer program product, system, and method for training and using a vector encoder to determine vectors for sub-images of text in an image to subject to optical character recognition. A vector encoder is trained to encode images representing text into vectors in a vector space. Vectors of images representing similar text have a high degree of cohesion in the vector space. Vectors of images representing dissimilar text have a low degree of cohesion in the vector space. An input image is processed to determine sub-images of the input image that bound text represented in the input image. The sub-images are inputted to the vector encoder to output sub-image vectors. The vector encoder generates a search vector for search text. Optical character recognition is applied to at least one region of the input image including the sub-images having sub-image vectors matching the search vector.

Abstract: A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: Performing UCI multiplexing includes generating PUCCH resources Z at an L1 HP procedure and an L1 LP procedure. The L1 HP procedure and the L1 LP procedure results in a plurality of HP PUCCHs and LP PUCCHs, respectively. A modified procedure for Set Q to resources Z is performed with the plurality of HP PUCCHs and LP PUCCHs as inputs. The plurality of HP PUCCHs according to starting symbols is scanned to identify an earliest starting HP PUCCH. A PUCCH from the plurality of LP PUCCHs or HP PUCCHS that overlaps with the earliest starting HP PUCCH is collected. Inter-L1 priority multiplexing is performed on the earliest starting HP PUCCH and the collected PUCCH, which may result in a new HP PUCCH. The new HP PUCCH is inserted into the Set Q. The modified procedure is repeated until there is no overlap among the HP PUCCHs and the LP PUCCHs.

Abstract: A device for detecting a slot wedge, an air gap and a broken rotor bar is provided, where a sequential circuit generates double concurrent pulses; the sequential circuit is connected to driving power modules; the driving power modules are connected to front-end interface circuits; the front-end interface circuits convert the double concurrent pulses into corresponding magnetic-field pulses; the magnetic-field pulses are transmitted to power supply terminals on adjacent phases of stator windings through impedance matching pins and coupled at a corresponding coil, air gap and squirrel cage rotor to generate single groups of cyclic rotating magnetic potentials; single rotating magnetic potentials are sequentially generated in adjacent slots on each of the phases of the stator windings; rotating electric potentials in magnetic circuits with two symmetrical phases are magnetically coupled to form distributed coupling magnetic field reflected full-cycle waves for reflecting a difference of a corresponding slot wedg

Abstract: A data processing method includes: generating a service serial number for a target service according to a preset naming rule; obtaining service data of the target service; obtaining a target data table from a plurality of pre-configured data tables, according to the service serial number; and storing the service data to the target data table.

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.