Patents by Inventor Charan V. Surisetty
Charan V. Surisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055426Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: April 19, 2023Publication date: February 15, 2024Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Publication number: 20230299134Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.Type: ApplicationFiled: November 4, 2022Publication date: September 21, 2023Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 11664375Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: February 12, 2021Date of Patent: May 30, 2023Assignee: Tessera LLCInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 11522045Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.Type: GrantFiled: March 1, 2021Date of Patent: December 6, 2022Assignee: TESSERA LLCInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20210210596Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.Type: ApplicationFiled: March 1, 2021Publication date: July 8, 2021Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheno Seo, Charan V. Surisetty
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Publication number: 20210183856Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: February 12, 2021Publication date: June 17, 2021Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 11037875Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: GrantFiled: March 26, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Patent number: 11031337Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: GrantFiled: June 19, 2019Date of Patent: June 8, 2021Assignee: International Business Machines CorporationInventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Patent number: 11011429Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: GrantFiled: September 3, 2020Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 10923471Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: March 8, 2019Date of Patent: February 16, 2021Assignee: Tessera, Inc.Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 10896816Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.Type: GrantFiled: September 26, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhenxing Bi, Thamarai S. Devarajan, Nicolas J. Loubet, Binglin Miao, Muthumanickam Sankarapandian, Charan V. Surisetty, Chun W. Yeung, Jingyun Zhang
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Publication number: 20200402860Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 10804159Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: GrantFiled: October 18, 2019Date of Patent: October 13, 2020Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20200051866Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 10559530Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: GrantFiled: December 27, 2017Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Patent number: 10490454Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: GrantFiled: June 28, 2018Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20190311986Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: ApplicationFiled: June 19, 2019Publication date: October 10, 2019Inventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Patent number: 10381458Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.Type: GrantFiled: November 25, 2015Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
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Publication number: 20190221519Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Publication number: 20190206865Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty