Patents by Inventor Charan V. Surisetty
Charan V. Surisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190198444Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
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Patent number: 10276569Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: March 16, 2018Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Publication number: 20190096669Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Zhenxing Bi, Thamarai S. Devarajan, Nicolas J. Loubet, Binglin Miao, Muthumanickam Sankarapandian, Charan V. Surisetty, Chun W. Yeung, Jingyun Zhang
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Patent number: 10177240Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.Type: GrantFiled: September 18, 2015Date of Patent: January 8, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
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Publication number: 20180323109Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: ApplicationFiled: June 28, 2018Publication date: November 8, 2018Inventors: Injo OK, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 10074569Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: GrantFiled: May 17, 2017Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20180204837Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: March 16, 2018Publication date: July 19, 2018Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 10014220Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.Type: GrantFiled: November 4, 2016Date of Patent: July 3, 2018Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita
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Patent number: 10014295Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.Type: GrantFiled: November 4, 2016Date of Patent: July 3, 2018Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita
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Patent number: 9985024Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: April 24, 2017Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 9972620Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.Type: GrantFiled: August 11, 2016Date of Patent: May 15, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Charan V. Surisetty, Dominic J. Schepis, Kangguo Cheng, Alexander Reznicek
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Patent number: 9953976Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.Type: GrantFiled: January 10, 2017Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 9917089Abstract: A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.Type: GrantFiled: October 4, 2016Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hemanth Jagannathan, Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty
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Publication number: 20180047727Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Charan V. SURISETTY, Dominic J. SCHEPIS, Kangguo CHENG, Alexander REZNICEK
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Patent number: 9893085Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.Type: GrantFiled: April 28, 2017Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 9852951Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: August 16, 2016Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Publication number: 20170323833Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: ApplicationFiled: May 17, 2017Publication date: November 9, 2017Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20170229459Abstract: A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.Type: ApplicationFiled: October 4, 2016Publication date: August 10, 2017Inventors: Hemanth Jagannathan, Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty
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Publication number: 20170229479Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.Type: ApplicationFiled: April 28, 2017Publication date: August 10, 2017Applicant: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20170229455Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty