Patents by Inventor Charan V. Surisetty
Charan V. Surisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9728626Abstract: A FinFET includes a fin and a conductive gate surrounding a top channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below a bottom surface of the conductive gate. The top channel region of the fin includes epitaxial semiconductor channel material that is at least majority defect free, the at least a majority of defects associated with forming the epitaxial semiconductor material in the channel region being trapped below a top portion of the channel region. The FinFET may be achieved by a method, the method including providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, semiconductor fin(s) on the bulk semiconductor substrate and surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s).Type: GrantFiled: August 30, 2016Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Dominic J. Schepis, Charan V. Surisetty, Kangguo Cheng, Alexander Reznicek
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Patent number: 9704760Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.Type: GrantFiled: June 24, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 9704753Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: July 7, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Publication number: 20170162445Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.Type: ApplicationFiled: November 4, 2016Publication date: June 8, 2017Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita
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Publication number: 20170162567Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.Type: ApplicationFiled: November 4, 2016Publication date: June 8, 2017Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita
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Patent number: 9673101Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: GrantFiled: September 30, 2015Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20170148789Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.Type: ApplicationFiled: January 10, 2017Publication date: May 25, 2017Inventors: Injo Ok, Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 9627322Abstract: A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.Type: GrantFiled: August 18, 2015Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Balasubramanian S. Pranatharthiharan, Charan V. Surisetty
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Publication number: 20170092543Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20170084463Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.Type: ApplicationFiled: September 18, 2015Publication date: March 23, 2017Inventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
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Publication number: 20170084723Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.Type: ApplicationFiled: November 25, 2015Publication date: March 23, 2017Inventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
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Patent number: 9601482Abstract: Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.Type: GrantFiled: December 8, 2015Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty
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Patent number: 9564370Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.Type: GrantFiled: October 20, 2015Date of Patent: February 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Publication number: 20160379893Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
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Patent number: 9520500Abstract: A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.Type: GrantFiled: December 7, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty, Soon-Cheon Seo, Tenko Yamashita
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Publication number: 20160358824Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 9515073Abstract: A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.Type: GrantFiled: February 8, 2016Date of Patent: December 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hemanth Jagannathan, Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty
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Publication number: 20160315144Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: ApplicationFiled: July 7, 2016Publication date: October 27, 2016Inventors: KANGGUO CHENG, BALASUBRAMANIAN PRANATHARTHIHARAN, ALEXANDER REZNICEK, CHARAN V. SURISETTY
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Patent number: 9443853Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: April 7, 2015Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Publication number: 20160148872Abstract: A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.Type: ApplicationFiled: August 18, 2015Publication date: May 26, 2016Inventors: Injo Ok, Balasubramanian S. Pranatharthiharan, Charan V. Surisetty