Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6429069
    Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed on a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, John K. Zahurak
  • Patent number: 6420250
    Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: July 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Chih-Chen Cho, Richard H. Lane, Charles H. Dennison
  • Publication number: 20020089034
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Application
    Filed: February 8, 2002
    Publication date: July 11, 2002
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Patent number: 6414392
    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: July 2, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 6410951
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: June 25, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Publication number: 20020076865
    Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
    Type: Application
    Filed: February 7, 2002
    Publication date: June 20, 2002
    Inventors: Charles H. Dennison, Monte Manning
  • Patent number: 6406977
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: June 18, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Publication number: 20020070422
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Application
    Filed: February 14, 2002
    Publication date: June 13, 2002
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Patent number: 6380596
    Abstract: In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: April 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Michael P. Violette, Charles H. Dennison
  • Patent number: 6376287
    Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect, transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Monte Manning
  • Patent number: 6376358
    Abstract: A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Jigish D. Trivedi, Charles H. Dennison, Todd R. Abbott, Raymond A. Turi
  • Patent number: 6372601
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: April 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Patent number: 6358787
    Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: March 19, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Mark Helm
  • Publication number: 20020031875
    Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 14, 2002
    Inventors: Kunal R. Parekh, Charles H. Dennison, Jeffrey W. Honeycutt
  • Publication number: 20020025644
    Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 28, 2002
    Inventors: Chih-Chen Cho, Richard H. Lane, Charles H. Dennison
  • Patent number: 6350638
    Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Charles H. Dennison
  • Publication number: 20020020883
    Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti
    Type: Application
    Filed: October 3, 2001
    Publication date: February 21, 2002
    Applicant: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20020013047
    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
    Type: Application
    Filed: September 18, 2001
    Publication date: January 31, 2002
    Inventor: Charles H. Dennison
  • Patent number: 6333254
    Abstract: In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Michael P. Violette, Charles H. Dennison
  • Patent number: 6331725
    Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: December 18, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison