Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030003691
    Abstract: A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion.
    Type: Application
    Filed: June 30, 2001
    Publication date: January 2, 2003
    Inventors: Charles H. Dennison, Guy C. Wicker, Tyler A. Lowrey, Stephen J. Hudgens, Chien Chiang, Daniel Xu
  • Publication number: 20030003634
    Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.
    Type: Application
    Filed: June 30, 2001
    Publication date: January 2, 2003
    Inventors: Tyler A. Lowrey, Charles H. Dennison
  • Patent number: 6501114
    Abstract: The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: December 31, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Chih-Chen Cho, Richard H. Lane, Charles H. Dennison
  • Patent number: 6498375
    Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: December 24, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 6482707
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: November 19, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Patent number: 6479332
    Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: November 12, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Monte Manning
  • Patent number: 6476490
    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: November 5, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20020160574
    Abstract: Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
    Type: Application
    Filed: April 27, 2001
    Publication date: October 31, 2002
    Inventors: John K. Zahurak, Brent Keeth, Charles H. Dennison
  • Patent number: 6468859
    Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: October 22, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Charles H. Dennison, Jeffrey W. Honeycutt
  • Patent number: 6468883
    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 22, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20020151135
    Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.
    Type: Application
    Filed: June 13, 2002
    Publication date: October 17, 2002
    Inventors: Kunal R. Parekh, Charles H. Dennison, Jeffrey W. Honeycutt
  • Patent number: 6465331
    Abstract: A DRAM having bi-level digit lines is fabricated on a silicon-on-insulator (“SOI”) substrate. More specifically, the digit lines of each complimentary digit line pair are positioned on opposite sides of the SOI substrate. In one embodiment, digit lines are formed between memory cell capacitors, and in a second embodiment, digit lines are formed above the capacitors.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 15, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Charles H. Dennison
  • Publication number: 20020132467
    Abstract: A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.
    Type: Application
    Filed: January 14, 2002
    Publication date: September 19, 2002
    Inventors: Mark Fischer, Jigish D. Trivedi, Charles H. Dennison, Todd R. Abbott, Raymond A. Turi
  • Publication number: 20020130395
    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
    Type: Application
    Filed: May 1, 2002
    Publication date: September 19, 2002
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 6445636
    Abstract: A method and system for refreshing a dynamic random access memory (“DRAM”) includes a pair of memory arrays for each of a plurality of banks. The DRAM includes the usual addressing and data path circuitry, as well as a refresh controller that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM can be used in place of an SRAM as a cache memory. Since only one of the arrays in each bank is refreshed at a time, the refresh controller is able to allow data to be written to the array that is not being refreshed. The refresh controller then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Kevin J. Ryan, Charles H. Dennison
  • Patent number: 6444520
    Abstract: A method of fabricating conductive plugs of different conductive types in contact with different conductivity type semiconductor regions of a semiconductor substrate. The method of the present invention utilizes a simplified two-step masking process and results in a semiconductor device having low resistance conductive plugs of two different conductivity types. The conductive plugs may be formed from conductive materials such as doped polysilicon or refractory metal. If a refractory metal is used, a barrier layer of titanium nitride or titanium oxynitride is used to form the outer layer of the conductive plug.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Raymond A. Turi
  • Publication number: 20020117707
    Abstract: The invention includes field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry. In one implementation, a field effect transistor includes a pair of source/drain regions having a channel region positioned therebetween. A gate is positioned operatively proximate the channel region, and includes conductively doped semiconductive material, a silicide layer and a conductive diffusion barrier layer. In another implementation, integrated circuitry comprises a field effect transistor having a gate, a gate dielectric layer, source/drain regions and a channel region. The gate comprises semiconductive material conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer. Insulative material is provided proximate the gate, and includes semiconductive material therein which is in electrical connection with the gate.
    Type: Application
    Filed: April 24, 2002
    Publication date: August 29, 2002
    Inventor: Charles H. Dennison
  • Publication number: 20020117752
    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
    Type: Application
    Filed: May 1, 2002
    Publication date: August 29, 2002
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 6440850
    Abstract: A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Mark Fischer, Charles H. Dennison
  • Patent number: RE37865
    Abstract: A semiconductor metallization processing method for multi-level electrical interconnection includes: a) providing a base insulating layer atop a semiconductor wafer; b) etching a groove pathway into the base layer; c) providing a first contact through the base layer to the area to which electrical connection is to be made; d) the groove pathway being etched and the first contact being provided in a combined manner which has the groove pathway and the first contact communicating with one another; e) providing metal within the first contact and within the groove pathway, the metal provided within the first contact and groove pathway in combination defining a first metal layer, the first metal layer having an overall thickness which is sufficient to fill the first contact and groove pathway; f) planarizing the first metal layer back to the uppermost region to form a conductive metal runner within the groove pathway; g) providing an overlying layer of insulating material which is different in composition from the
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: October 1, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison