Patents by Inventor Charles H. Wallace
Charles H. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666451Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.Type: GrantFiled: September 27, 2013Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Charles H. Wallace, Paul A. Nyhus
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Publication number: 20170139318Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Applicant: INTEL CORPORATIONInventors: CHARLES H. WALLACE, HOSSAM M. ABDALLAH, ELLIOT N. TAN, SWAMINATHAN SIVAKUMAR, OLEG GOLONZKA, ROBERT M. BIGWOOD
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Patent number: 9558947Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.Type: GrantFiled: December 29, 2011Date of Patent: January 31, 2017Assignee: INTEL CORPORATIONInventors: Charles H. Wallace, Hossam M. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood
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Publication number: 20170018499Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.Type: ApplicationFiled: May 8, 2014Publication date: January 19, 2017Inventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
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Publication number: 20160204002Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Applicant: Intel CorporationInventors: CHARLES H. WALLACE, PAUL A. NYHUS
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Publication number: 20160197011Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.Type: ApplicationFiled: September 27, 2013Publication date: July 7, 2016Inventors: ROBERT L. BRISTOL, FLORIAN GSTREIN, RICHARD E. SCHENKER, PAUL A. NYHUS, CHARLES H. WALLACE, HUI JAE YOO
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Publication number: 20160190009Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.Type: ApplicationFiled: September 27, 2013Publication date: June 30, 2016Applicant: Intel CorporationInventors: CHARLES H. WALLACE, PAUL A. NYHUS, ELLIOT N. TAN, SWAMINATHAN SIVAKUMAR
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Patent number: 9285682Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: GrantFiled: March 9, 2015Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
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Patent number: 9224602Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.Type: GrantFiled: December 29, 2011Date of Patent: December 29, 2015Assignee: INTEL CORPORATIONInventors: Aravind S. Killampalli, Charles H. Wallace, Bernhard Sell
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Patent number: 9142421Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: GrantFiled: December 29, 2011Date of Patent: September 22, 2015Assignee: INTEL CORPORATIONInventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi
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Publication number: 20150253667Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: ApplicationFiled: March 9, 2015Publication date: September 10, 2015Applicant: INTEL CORPORATIONInventors: ROBERT L. BRISTOL, PAUL A. NYHUS, CHARLES H. WALLACE
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Publication number: 20150187592Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.Type: ApplicationFiled: March 13, 2015Publication date: July 2, 2015Inventors: Fitih M. CINNOR, Charles H. WALLACE
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Patent number: 9046761Abstract: Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension.Type: GrantFiled: March 18, 2013Date of Patent: June 2, 2015Assignee: INTEL CORPORATIONInventors: Shem O. Ogadhoh, Charles H. Wallace, Ryan Pearman, Sven Henrichs, Arvind Sundaramurthy, Swaminathan Sivakumar
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Patent number: 9005875Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: GrantFiled: March 15, 2013Date of Patent: April 14, 2015Assignee: Intel CorporationInventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
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Patent number: 8980757Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.Type: GrantFiled: December 15, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Fitih M. Cinnor, Charles H. Wallace
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Publication number: 20140272711Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: ROBERT L. BRISTOL, PAUL A. NYHUS, CHARLES H. WALLACE
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Publication number: 20140117488Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.Type: ApplicationFiled: December 29, 2011Publication date: May 1, 2014Inventors: Charles H. Wallace, Hossam M. Abdallah, Elliot N. Tan, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood
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Publication number: 20140117489Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.Type: ApplicationFiled: December 29, 2011Publication date: May 1, 2014Inventors: Aravind S. Killampalli, Charles H. Wallace, Bernhard Sell
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Publication number: 20140073137Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.Type: ApplicationFiled: December 15, 2011Publication date: March 13, 2014Inventors: Fitih M. Cinnor, Charles H. Wallace
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Publication number: 20140017899Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.Type: ApplicationFiled: December 29, 2011Publication date: January 16, 2014Inventors: Charles H. Wallace, Swaminathan Sivakumar, Matthew L. Tingey, Chanaka D. Munasinghe, Nadia M. Rahhal-Orabi