Abstract: A method of manufacturing a semiconductor device of the "planar" type comprising a highly doped substrate having a doping concentration c.sub.o and an epitaxial surface layer having a carrier concentration c<c.sub.o, in which are formed a main pn junction having a depth x.sub.j and a structure of floating guard rings. According to the invention, this device also includes between the substrate and the epitaxial surface layer, a second epitaxial layer having a carrier concentration c' such that c.sub.o >c'>c. This permits the production of devices with different maximum operating voltages using the same configuration of guard rings.

Abstract: A vertical MOS-FET device having a planar multicell structure which is constituted by an assembly of elementary cells of a polygonal form having a source zone, a shortcircuit region, a channel zone and a drain zone. In the space between adjoining apices of a number of elementary cells there are provided complementary elements having a construction similar to that of the previously-mentioned cells but having a polygonal form adapted to the configuration of the cells. Thus, the overall length of the channel zones per unit surface area can be optimized.