Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: A display device includes a plurality of first pixels, a plurality of second pixels, a plurality of first multiplexers, a plurality of second multiplexers, a plurality of first traces, a plurality of second traces, and an integrated circuit. First multiplexers are used to control first pixels. Second multiplexers are used to control second pixels. First traces are coupled to each of first multiplexers. Second traces are coupled to each of second multiplexers. Integrated circuit includes at least two first polarity pins s and at least two second polarity pins. At least two first polarity pins s are adjacent. At least two second polarity pins are adjacent. At least two first polarity pins and at least two second polarity pins are arranged alternately. At least two first polarity pins s are coupled to first traces. At least two second polarity pins are coupled to second traces.

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current to illuminate one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A pixel circuit includes a liquid crystal capacitor, a memory circuit, a driving circuit, a mode-switching circuit, and a control circuit. The memory circuit is configured to store a status signal. The driving circuit includes a first terminal configured to receive a data voltage and a second terminal electrically coupled to a first terminal of the liquid crystal capacitor, and the driving circuit is configured to be ON or OFF according to a scan signal selectively. The mode-switching circuit is configured to be ON or OFF according to a mode-switching signal selectively. The control signal is electrically coupled to the mode-switching circuit at a first node, and is configured to control the voltage level of the first node corresponding to the status signal, and output a display voltage to the liquid crystal capacitor via the mode-switching circuit when the mode-switching circuit is ON.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Abstract: A light-emitting diode display device and a light-emission control method thereof are provided. The light-emitting diode display device includes a timing controller, multiple display pixels, and a scanning circuit. The display pixels form multiple display rows. The scanning circuit generates multiple scan signals and multiple light-emission signals that respectively drive the display rows. During a first data-writing time period of a first frame period, the timing controller provides multiple writing data to be respectively written into the display rows. During a light-emitting time period, the scanning circuit drives each of the light-emission signals to generate multiple pulses periodically according to a set period to drive the corresponding display rows. The light-emitting time period is after the first data-writing time period and before a second data-writing time period of a second frame period ends.

Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.

Abstract: A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Abstract: A multiplexer circuit and a display panel having the multiplexer circuit are provided. The multiplexer circuit includes a plurality of first transistors, a plurality of first control lines, a plurality of second control lines, a plurality of first transmission lines, and a plurality of second transmission lines. The first transistors are sequentially arranged along a first direction. The first control lines extend along the first direction and are disposed on a first side of the first transistors. The second control lines extend along the first direction and are disposed on a second side of the first transistors. The first transmission lines are respectively coupled between control terminals of a first group of the first transistors and the first control lines. The second transmission lines are respectively coupled to control terminals of a second group of the first transistors and the second control lines.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: A display device includes a substrate and pixels. The substrate has an intermediate region and a peripheral region. Each of the pixels includes sub-pixels. Each of the sub-pixels includes a pad group and a light emitting diode (LED) element. The pad group has a first pad and a second pad. The LED element is electrically connected to the first pad and the second pad. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. The first pads and the second pads of the pad groups of the sub-pixels of each of the standard pixels are arranged in a first direction. The peripheral pixels include a first peripheral pixel. The first pads and the second pads of the pad groups of the sub-pixels of the first peripheral pixel are arranged in a second direction, and the first direction crosses over the second direction.

Abstract: A display device includes a pixel array substrate, a sensing element substrate, and a display medium layer. The display medium layer is disposed between the pixel array substrate and the sensing element substrate. The sensing element substrate includes a substrate, a switch element, an insulation layer, an electrically conductive layer, a signal line, a sensing layer, and an electrode layer. The switch element is disposed on the substrate. The insulation layer covers the switch element. The electrically conductive layer is disposed on the insulation layer. The signal line is electrically connected to the electrically conductive layer. The sensing layer covers a top surface of the electrically conductive layer, a first side of the electrically conductive layer, and a second side of the electrically conductive layer. The electrode layer covers the sensing layer. The electrode layer is electrically connected to the switching element.

Abstract: An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

Abstract: A display apparatus includes pixels, each of which includes first and second pixel driver circuits, first and second driver pads electrically connected to the first and second pixel driver circuits, respectively, a first LED element, first and second connection lines electrically connected to the first and second pixel driver circuits, respectively, and first and second repair pads electrically connected to the first and second connection lines, respectively. A first electrode of the first LED element is electrically connected to the first driver pad. The first repair pad, the second repair pad, the first driver pad, and the second driver pad are structurally separated. A first pixel of the pixels further includes a second LED element overlapping the first and second repair pads of the first pixel, and a first electrode of the second LED element is electrically connected to the second repair pad.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Abstract: A display panel and a pixel circuit thereof are provided. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits. Each of the pixel circuits is coupled to corresponding gate line and data line. Each of the pixel circuits includes a first gate line and a pull-low switch. The first gate line is coupled to a control terminal of a driving transistor, and provides a first gate signal to drive the driving transistor during a driving time period. The pull-low switch pulls low the first gate signal to a reference low voltage according to a second gate signal on a second gate line when the driving time period finishes.