Abstract: A touch display panel includes a touch circuit, a touch electrode layer and a plurality of multiplexers. The touch electrode layer includes a plurality of first electrodes. Each of the multiplexers is electrically connected to the touch circuit and the first electrodes. Each of the multiplexers is configured to output a touch sensing signal, a first guarding signal and a second guarding signal according to a first guarding control signal, a second guarding control signal, a first touch control signal, and a second touch control signal.

Abstract: A display driving circuit is provided. The display driving circuit includes: at least one gate driving circuit, each of the at least one gate driving circuit generating a driving signal so that display pixels update pixel data according to each of the driving signals; and at least two enable-selecting circuits, generating a zone start-updating signal and a zone end-updating signal according to a zone scan-control signal and the driving signals and enabling the at least one gate driving circuit of a first portion according to the zone start-updating signal and the zone end-updating signal. In this way, the at least one gate driving circuit of the first portion generates the driving signals to update part of the display pixels, and that power saving is achieved.

Abstract: A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

Abstract: A heat dissipation system and a coolant distribution module for plural electronic components of an electronic computing device are provided. The heat dissipation system includes plural water-cooling heads, a heat dissipation device and the coolant distribution module. When a fluid medium flows through the heat dissipation device, the heat dissipation device exchanges heat with the fluid medium. The coolant distribution module is connected between the plural water-cooling heads and the heat dissipation device. The coolant distribution module includes a main body and a power module. The module main body includes a cooled fluid chamber. The cooled fluid chamber includes plural first outlets corresponding to the plural water-cooling heads. The power module is installed in the module main body. The power module drives the fluid medium to be outputted from the plural first outlets. Consequently, the fluid medium is transferred through a circulating loop.

Abstract: A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: A pixel structure disposed on a substrate having a pixel sensor region and a pixel display region disposed beside the pixel sensor region is provided. The pixel structure includes a pixel defining layer, a light-emitting diode, a pixel driving circuit and a sensor device. The pixel defining layer is disposed on the substrate and has a device accommodation portion located in the pixel display region. The light-emitting diode is disposed on the device accommodation portion. The area of the light-emitting diode is smaller than that of the device accommodation portion. The pixel driving circuit is disposed on the substrate, is electrically connected to the light-emitting diode, and includes a pixel electrode by which the device accommodation portion is covered. The light-emitting diode is bonded onto the pixel electrode. The sensor device is disposed between the pixel defining layer and the substrate and located in the pixel sensor region.

Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Abstract: A touch display panel having a display region, a peripheral region surrounding the display region, and a sensing region located between the display region and the peripheral region is provided. The touch display panel includes a pixel array, a touch electrode, an active device, at least one first sensor, at least one second sensor, and a light-shielding layer. The pixel array is located in the display region. The touch electrode located in the sensing region and the pixel array are separated from each other. The active device coupled to the touch electrode is located in the sensing region. The at least one first sensor and the at least one second sensor are located in the sensing region and separated from each other. The light-shielding layer covers the at least one first sensor.

Abstract: A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.

Abstract: A touch display panel includes a touch circuit, a touch electrode layer and a plurality of multiplexers. The touch electrode layer includes a plurality of first electrodes. Each of the multiplexers is electrically connected to the touch circuit and the first electrodes. Each of the multiplexers is configured to output a touch sensing signal, a first guarding signal and a second guarding signal according to a first guarding control signal, a second guarding control signal, a first touch control signal, and a second touch control signal.

Abstract: A pixel structure includes a scan line, a data line, a switching element, a planarization layer, a first common electrode, a common line, a first insulating layer, a pixel electrode, a second insulating layer, and a second common electrode. The switching element includes a source and a drain. The common line is located on the planarization layer and directly connected with the first common electrode. The planarization layer is located on the scan line, the data line, and the switching element. The pixel electrode is electrically connected with the drain through a first contact hole, wherein the first contact hole penetrates through the planarization layer and the first insulating layer. The second common electrode is electrically connected with the first common electrode through a second contact hole, wherein the second contact hole penetrates through the first insulating layer and the second insulating layer. A touch panel is also provided.

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: A display apparatus includes a plurality of pixel lines, a multiplexer, a first switch and a second switch. The pixel lines are respectively coupled to a plurality of data lines. The data lines include a first selected data line, a second selected data line and a plurality of other data lines. The first switch is coupled between the first selected data line and a first non-selected data line among the other data lines and is turned on or turned off according to a first control signal. The second switch is coupled between the first selected data line and a second non-selected data line among the other data lines and is turned on or cut off according to a second control signal.

Abstract: A display driving circuit is provided. The display driving circuit includes: at least one gate driving circuit, each of the at least one gate driving circuit generating a driving signal so that display pixels update pixel data according to each of the driving signals; and at least two enable-selecting circuits, generating a zone start-updating signal and a zone end-updating signal according to a zone scan-control signal and the driving signals and enabling the at least one gate driving circuit of a first portion according to the zone start-updating signal and the zone end-updating signal. In this way, the at least one gate driving circuit of the first portion generates the driving signals to update part of the display pixels, and that power saving is achieved.

Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

Abstract: A display device includes a pixel array substrate, a sensing element substrate, and a display medium layer. The display medium layer is disposed between the pixel array substrate and the sensing element substrate. The sensing element substrate includes a substrate, a switch element, an insulation layer, an electrically conductive layer, a signal line, a sensing layer, and an electrode layer. The switch element is disposed on the substrate. The insulation layer covers the switch element. The electrically conductive layer is disposed on the insulation layer. The signal line is electrically connected to the electrically conductive layer. The sensing layer covers a top surface of the electrically conductive layer, a first side of the electrically conductive layer, and a second side of the electrically conductive layer. The electrode layer covers the sensing layer. The electrode layer is electrically connected to the switching element.