Patents by Inventor Che Hao Chang

Che Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240100880
    Abstract: A multi-piece wheel frame includes a rim and a disc. The rim includes a barrel, and an outer rim portion protruding outwardly from the barrel. The outer rim portion forms an inclined surface, and a ring edge surface connected to an outer edge of the inclined surface and cooperating with the inclined surface to form an obtuse angle. The disc is fixed to the rim, and includes a disc core, a plurality of spoke portions extending radially outwardly from the disc core, and a reinforced ring portion connected to the spoke portions and fixed to the outer rim portion. The reinforced ring portion abuts against at least one of the inclined surface and the ring edge surface.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 28, 2024
    Inventors: Te-Fu HSIAO, Che-Hao KUO, Chung-Hsin CHANG, Chia-Hsin WANG, Erh-Wei LIU
  • Patent number: 11942329
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11923432
    Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
  • Publication number: 20240071825
    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
  • Patent number: 11916132
    Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11901439
    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20240021706
    Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 18, 2024
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Szu-Ying Chen
  • Publication number: 20230387275
    Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Te-Yang Lai, Che-Hao Chang, Chi On Chui
  • Patent number: 11824104
    Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flow able oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Yang Lai, Che-Hao Chang, Chi On Chui
  • Publication number: 20230369428
    Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 16, 2023
    Inventors: Chih-Hung Sun, Wen-Kai Lin, Che-Hao Chang, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20230361201
    Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked, removing edge portions of the second semiconductor layers to form cavities between adjacent first semiconductor layers, selectively forming a passivation layer on sidewalls of the first semiconductor layers, forming a dielectric spacer on sidewalls of the second semiconductor layers and filling in the cavities, wherein the passivation layer is exposed. The method also includes removing the passivation layer, and forming an epitaxial source/drain feature so that the epitaxial source/drain feature is in contact with the first semiconductor layers and the dielectric spacers.
    Type: Application
    Filed: May 7, 2022
    Publication date: November 9, 2023
    Inventors: Wen-Kai LIN, Che-Hao CHANG, Yoh-Rong LIU, Zhen-Cheng WU, Chi On CHUI
  • Publication number: 20230352568
    Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 2, 2023
    Inventors: Wan-Yi Kao, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui, Hung Cheng Lin
  • Publication number: 20230290853
    Abstract: A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Jin LI, Che-Hao CHANG, Zhen-Cheng WU, Chi On CHUI
  • Patent number: 11757020
    Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230275140
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 31, 2023
    Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
  • Publication number: 20230268426
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 24, 2023
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230268416
    Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20230261045
    Abstract: Semiconductor devices including air gaps between source/drain regions and a semiconductor substrate and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source/drain region adjacent the gate structure and the first channel region; a first inner spacer layer between the first source/drain region and the semiconductor substrate in a first direction perpendicular to a major surface of the semiconductor substrate; and a first air gap between the first source/drain region and the first inner spacer layer in the first direction.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 17, 2023
    Inventors: Wen-Kai Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230261080
    Abstract: A method includes forming a stack of layers comprising a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a first spacer layer extending into the lateral recesses, with the first spacer layer comprising a first dielectric material, depositing a second spacer layer on the first spacer layer, with the second spacer layer comprising a second dielectric material different from the first dielectric material, and trimming the first spacer layer and the second spacer layer to form inner spacers.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 17, 2023
    Inventors: Wen-Kai Lin, Tzu-Chieh Su, Che-Hao Chang
  • Patent number: 11710782
    Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui