Patents by Inventor Che Hao Chang
Che Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10964543Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.Type: GrantFiled: November 4, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Publication number: 20210057540Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flow able oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.Type: ApplicationFiled: August 20, 2019Publication date: February 25, 2021Inventors: Te-Yang Lai, Che-Hao Chang, Chi On Chui
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Publication number: 20210028285Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.Type: ApplicationFiled: July 28, 2019Publication date: January 28, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
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Patent number: 10879371Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.Type: GrantFiled: June 12, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang
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Patent number: 10867869Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: GrantFiled: November 18, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
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Publication number: 20200083115Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: ApplicationFiled: November 18, 2019Publication date: March 12, 2020Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
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Publication number: 20200066535Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Patent number: 10540697Abstract: Embodiments of the invention include methods and systems for a styling platform. In one embodiment, a method is implemented in a beauty application of a mobile device. The method includes applying a styling feature to a facial image through the beauty application, the method further includes transmitting a message from a first user to a second user through the beauty application, the message containing a hyperlink to the facial image with the styling feature applied. The method further includes establishing a communication session within the beauty application between the first and second users responsive to receiving a reply from the second user, and exchanging information regarding the styling feature within the beauty application between the first and second users using the communication session.Type: GrantFiled: June 23, 2017Date of Patent: January 21, 2020Assignee: PERFECT365 TECHNOLOGY COMPANY LTD.Inventors: Kaixuan Mao, Chiachi Wei, Che-Hao Chang, Hui Deng, Wanjiang Wang
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Publication number: 20200006157Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
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Publication number: 20190378913Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang
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Patent number: 10504795Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: GrantFiled: March 27, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
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Patent number: 10468258Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.Type: GrantFiled: June 12, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Da Lin, Che-Hao Chang, Cheng-Hao Hou, Xiong-Fei Yu
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Patent number: 10453933Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.Type: GrantFiled: October 27, 2016Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
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Publication number: 20190304846Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Yu LEE, Huicheng CHANG, Che-Hao CHANG, Ching-Hwanq SU, Weng CHANG, Xiong-Fei YU
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Publication number: 20190296448Abstract: A signal line conversion structure of the antenna array is disposed between the antenna array and the circuit substrate, which includes a first dielectric substrate is disposed on the circuit substrate, a second dielectric substrate is vertically disposed on the first dielectric substrate and divided into a first region and a second region, and the second dielectric substrate is provided with the antenna array. At least one signal line is disposed on the first region and extends to the second dielectric substrate for connecting the circuit substrate and the antenna array. A metal connecting plate has at least three metal through holes pierced in the first dielectric substrate and connected to the second ground layer. The metal connecting plate is connected to the first ground layer of the first dielectric substrate and the second ground layer of the second dielectric substrate through the metal through holes.Type: ApplicationFiled: June 25, 2018Publication date: September 26, 2019Inventors: Jenn-Hwan TARNG, Chi-Yang CHANG, Che-Hao CHANG, Jing-Cheng HONG
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Patent number: 10418720Abstract: A signal line conversion structure of the antenna array is disposed between the antenna array and the circuit substrate, which includes a first dielectric substrate is disposed on the circuit substrate, a second dielectric substrate is vertically disposed on the first dielectric substrate and divided into a first region and a second region, and the second dielectric substrate is provided with the antenna array. At least one signal line is disposed on the first region and extends to the second dielectric substrate for connecting the circuit substrate and the antenna array. A metal connecting plate has at least three metal through holes pierced in the first dielectric substrate and connected to the second ground layer. The metal connecting plate is connected to the first ground layer of the first dielectric substrate and the second ground layer of the second dielectric substrate through the metal through holes.Type: GrantFiled: June 25, 2018Date of Patent: September 17, 2019Assignee: National Chiao Tung UniversityInventors: Jenn-Hwan Tarng, Chi-Yang Chang, Che-Hao Chang, Jing-Cheng Hong
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Patent number: 10367078Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.Type: GrantFiled: January 22, 2018Date of Patent: July 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Yuan Chang, Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
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Publication number: 20190140082Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shieling layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.Type: ApplicationFiled: January 22, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Yuan Chang, Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
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Publication number: 20180374128Abstract: Embodiments of the invention include methods and systems for a styling platform. In one embodiment, a method is implemented in a beauty application of a mobile device. The method includes applying a styling feature to a facial image through the beauty application, the method further includes transmitting a message from a first user to a second user through the beauty application, the message containing a hyperlink to the facial image with the styling feature applied. The method further includes establishing a communication session within the beauty application between the first and second users responsive to receiving a reply from the second user, and exchanging information regarding the styling feature within the beauty application between the first and second users using the communication session.Type: ApplicationFiled: June 23, 2017Publication date: December 27, 2018Inventors: Kaixuan Mao, Chiachi Wei, Che-Hao Chang, Hui Deng, Wanjiang Wang
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Patent number: 9866061Abstract: A power supply apparatus with a protection function includes a pulse width modulation control unit, a pulse width modulation detecting unit, a switch unit and a feedback circuit. The feedback circuit detects a bus voltage. When the feedback circuit detects that the bus voltage is greater than a predetermined voltage, the feedback circuit sends an informing signal to the pulse width modulation control unit. The pulse width modulation control unit adjusts a duty cycle of a pulse width modulation signal and sends the pulse width modulation signal to the pulse width modulation detecting unit. When the pulse width modulation detecting unit detects that the duty cycle of the pulse width modulation signal is less than a predetermined cycle, the pulse width modulation detecting unit turns off the switch unit to stop outputting power to avoid a reverse current phenomenon.Type: GrantFiled: November 20, 2015Date of Patent: January 9, 2018Assignee: Chicony Power Technology Co., Ltd.Inventors: Tzu-Hung Wang, Wei-Yuan Chen, Che-Hao Chang, Zhi-Hong Lu, Hai-Wen Chang