Abstract: A memory storage apparatus including a memory array and a controller circuit is provided. The memory array is configured to store a first error correcting code and a first data. The controller circuit is coupled to the memory array. The controller circuit is configured to read the first data from the memory array and determine whether an error bit of the first data is one of one or more data mask bits to decide whether to update the first error correcting code stored in the memory array. The controller circuit includes a switch element. The switch element is coupled to the memory array. The switch element receives the first data from the memory array. An error correcting procedure is not performed on the first data. In addition, a data access method is also provided.

Abstract: A pixel structure includes a first, second and third electrode layers and a switch element. The second electrode layer is disposed above the first electrode layer and includes a first and second main body portions and a first and second branch portions. The first main body portion and the first branch portion extend in a first direction. The first branch portion protrudes from the first to second main body portion. The second branch portion protrudes from the second to first main body portion. The third electrode layer is disposed above the second electrode layer and includes a third and fourth main body portion and a third branch portion. The third and fourth main body portions extend in the first direction. The third branch portion connects the third to fourth main body portion. The switch element is electrically connected to the first or third electrode layer.

Abstract: A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.

Abstract: A control method is provided. The control method is applied to an electronic device. The control method includes the following steps: detecting a virtual screen signal; allocating a virtual screen image buffer module for temporarily storing virtual screen image information according to the virtual screen signal; integrating the virtual screen image information and second screen image information into an integrated image data stream by a direct mode; outputting a first screen image data stream to a first screen of an electronic device, so that the first screen displays a first image according to the first screen image data stream; and outputting the integrated image data stream to a second screen of the electronic device, so that the second screen displays a second image according to the integrated image data stream.

Abstract: A memory storage device and a memory testing method for testing a memory array of the memory storage device are provided. The memory testing method includes the following steps: writing first data into a plurality of first segments of the memory array, and writing second data to a second segment of the memory array; obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment; converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.

Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Abstract: A pixel structure includes a first, second and third electrode layers and a switch element. The second electrode layer is disposed above the first electrode layer and includes a first and second main body portions and a first and second branch portions. The first main body portion and the first branch portion extend in a first direction. The first branch portion protrudes from the first to second main body portion. The second branch portion protrudes from the second to first main body portion. The third electrode layer is disposed above the second electrode layer and includes a third and fourth main body portion and a third branch portion. The third and fourth main body portions extend in the first direction. The third branch portion connects the third to fourth main body portion. The switch element is electrically connected to the first or third electrode layer.

Abstract: A control method is provided. The control method is applied to an electronic device. The control method includes the following steps: detecting a virtual screen signal; allocating a virtual screen image buffer module for temporarily storing virtual screen image information according to the virtual screen signal; integrating the virtual screen image information and second screen image information into an integrated image data stream by a direct mode; outputting a first screen image data stream to a first screen of an electronic device, so that the first screen displays a first image according to the first screen image data stream; and outputting the integrated image data stream to a second screen of the electronic device, so that the second screen displays a second image according to the integrated image data stream.

Abstract: A data reading device and a data reading method for design-for-testing are provided. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge-triggered signal, a clock negative edge-triggered signal, a trigger mask signal, and test data. The data serialization circuit masks one of the clock positive edge-triggered signal and the clock negative edge-triggered signal according to the trigger mask signal, and provides a part of the test data to an output terminal of the data serialization circuit as an output signal of the data reading device according to the unmasked one of the clock positive edge-triggered signal and the clock negative edge-triggered signal. Thus, a data valid window of the test data can be increased.

Abstract: An oral cleaning detection system includes a remote data service platform and mobile smart device. The remote data service platform is built on a network platform including a tooth cleaning software module having a motion detection unit and reward unit; the mobile smart device may enter the remote data service platform to download the tooth cleaning software module, a photography equipment of the mobile smart device is turned on through the software to capture a user's teeth brushing motion, a motion track comparison is carried out with the tooth cleaning software module to judge whether a preset brushing motion is completed correctly, and at the same time, a user may be rewarded as an encouragement.

Abstract: A data reading device and a data reading method for design-for-testing are provided. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge-triggered signal, a clock negative edge-triggered signal, a trigger mask signal, and test data. The data serialization circuit masks one of the clock positive edge-triggered signal and the clock negative edge-triggered signal according to the trigger mask signal, and provides a part of the test data to an output terminal of the data serialization circuit as an output signal of the data reading device according to the unmasked one of the clock positive edge-triggered signal and the clock negative edge-triggered signal. Thus, a data valid window of the test data can be increased.

Abstract: A blockchain electronic medical record system includes a hospital clinic end and patient end, a doctor at the hospital clinic end generating medical record data after the diagnosis of a patient, writing each of medical records into a connected computer to form electronic medical records, and storing the electronic medical records into a web server; the hospital clinic end giving the patient a secret key; the patient end obtaining the secret key, using the key to obtain an electronic medical record file from a space in connection with the web server and having a right to access to the electronic medical record file.

Abstract: A blockchain dental implant system includes a doctor end and patient end, a doctor at the doctor end generating dental implant medical record data after the diagnosis of a dental implant patient, writing each of the medical records into a connected computer to form a dental implant file, and storing the dental implant file into a web server; the doctor end giving the patient a secret key; the patient end obtaining the secret key, using the key to obtain the dental implant file from a space in connection with the web server and having a right to access to the dental implant file.

Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Abstract: A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.

Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.

Abstract: A power gating circuit and a control method for power gating switch thereof are provided. The power gating circuit includes a first switch, the power gating switch, a pre-charge circuit, and a control circuit. A first terminal and a second terminal of the first switch are coupled to a first voltage and the control terminal of the power gating switch, respectively. A first terminal and a second terminal of the power gating switch are coupled to a second voltage and a function circuit, respectively. An input signal defines a powered period of the function circuit. According to the input signal, the pre-charge circuit pre-charges the control terminal of the power gating switch during the first sub-period of the powered period, and the control circuit controls the first switch to charge the control terminal of the power gating switch by the first voltage during the second sub-period of the powered period.

Abstract: A power gating circuit and a control method for power gating switch thereof are provided. The power gating circuit includes a first switch, the power gating switch, a pre-charge circuit, and a control circuit. A first terminal and a second terminal of the first switch are coupled to a first voltage and the control terminal of the power gating switch, respectively. A first terminal and a second terminal of the power gating switch are coupled to a second voltage and a function circuit, respectively. An input signal defines a powered period of the function circuit. According to the input signal, the pre-charge circuit pre-charges the control terminal of the power gating switch during the first sub-period of the powered period, and the control circuit controls the first switch to charge the control terminal of the power gating switch by the first voltage during the second sub-period of the powered period.

Abstract: Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises a calibration region configured to detect a color level for image reproduction, such as a black calibration region configured to detect a black level for an image detected by the photodiode array. The image sensor comprises a dielectric film that is formed over the photodiode array and the calibration region. The dielectric film is configured to balance stress between the photodiode and the calibration region in order to improve accuracy of the calibration region.

Abstract: This invention relates to a multi-rotor aircraft frame structure, which is mainly the use of stainless steel tubes and engineering plastics has the rigidity and toughness, directly to the stainless steel tubes symmetrical inserted nailed in plastic sheet to constitute the main frame structure, and by connecting plurality support blocks and plurality support rods to construct a kind of peripheral support structure to obtain sufficient structural strength, thereby to constructing a light weight and low cost and practicality high-performance multi-rotor aircraft frame.