Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.

Abstract: The disclosure provides a positive photoresist composition, comprising: a (A) polyimide resin, a (B) photo active compound and a (C) solvent. The (A) polyimide resin is obtained by a polymerization reaction of a (a) diamine and a (b) tetracarboxylic dianhydride, and has a structural unit of formula (1); wherein, Ar1 in the formula (1) is a tetravalent organic group, Ar2 is a bivalent organic group, and Ar1 is a group of formula (B-1), formula (B-2), formula (B-3) or a combination thereof, and Ar2 is at least a group of formula (A-1), formula (A-2) or a combination thereof. Furthermore, Ar2 can further be a group of formula (A-3), formula (A-4), formula (A-5) or a combination thereof. The present disclosure further provides a negative photoresist pattern lithography process method and a photoresist pattern thereof.

Abstract: A centrifugal fan module is provided. The centrifugal fan module includes a housing, a blade unit, a heat sink and a vapor chamber. The housing includes a bottom cover, a sidewall, a top cover and an outlet structure, wherein the bottom cover is connected to the bottom of the sidewall, the top cover is connected to the top of the sidewall, and the outlet structure is connected to the top cover and the sidewall. The blade unit is disposed in the housing, wherein the blade unit is located between the bottom cover and the top cover. The heat sink is disposed on the vapor chamber, the heat sink is located between the vapor chamber and the top cover, and the heat sink is located between the outlet structure and the blade unit.

Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.

Abstract: The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.

Abstract: Provided is an underground pipe leak detection system, including a sensing device, a storage device, and a processing device. The sensing device is used for collecting a voice signal from an underground pipe during a time period. The storage device is used for storing a voice dataset, and storing the voice signal transmitted by the sensing device. The processing device may access the storage device. The processing device is configured to execute the following operations: training a classification model using the voice dataset; extracting features of the voice signal; inputting the features of the voice signal into the classification model that has been trained to determine if there is a leak in the underground pipe.

Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

Abstract: An assembly structure includes an outer joint assembly and an inner joint assembly. At least one terminal portion of the outer joint assembly is hollow to form an accommodating space, the outer joint assembly includes an outer casing and at least one elastic sheet, the elastic sheet has a fixed end and a free end, the fixed end is connected to the outer casing, and the free end is provided with a first engaging part. The outer surface of the inner joint assembly is provided with a second engaging part, the inner joint assembly is used to extend into the accommodating space, and the first engaging part and the second engaging part are used to engage with each other. Through the above design, the assembly structure has quick connect capability, which makes it more convenient for users to use.

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

Abstract: An assembly structure includes an outer joint assembly and an inner joint assembly. At least one terminal portion of the outer joint assembly is hollow to form an accommodating space, the outer joint assembly includes an outer casing and at least one elastic sheet, the elastic sheet has a fixed end and a free end, the fixed end is connected to the outer casing, and the free end is provided with a first engaging part. The outer surface of the inner joint assembly is provided with a second engaging part, the inner joint assembly is used to extend into the accommodating space, and the first engaging part and the second engaging part are used to engage with each other. Through the above design, the assembly structure has quick connect capability, which makes it more convenient for users to use.

Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.