Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: In order to solve the problem of loosening that may occur in the assembly structure of the prior art when the user wants to rotate the inner joint assembly to change the light angle of the lighting device installed in the inner joint assembly during the rotation process, an embodiment of the present disclosure provides an assembly structure with a slot. In the present disclosure, only when a card part is inserted into the slot, can the inner joint assembly and outer joint assembly be allowed to be locked with or unlocked from each other by rotation, otherwise only the inner joint assembly can be rotated relative to the outer joint assembly, but both of them cannot be locked with or unlocked from each other by rotation.

Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.

Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals.

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

Abstract: A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original display data signal and outputs a first display data signal, the Nth stage LED driver receives a (N?1)th display data signal and outputs a Nth display data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to a first phase difference between the (N?1)th display data signal and the recovery clock signal; and a first transmitter outputting the Nth display data signal according to the recovery clock signal and the recovery data signal.

Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

Abstract: A magnetic assembly structure comprises a first main body and a second main body. The first main body comprises at least one first buckle structure. The second main body comprises a tail terminal portion, at least one magnetic attraction unit, at least one second buckle structure and at least one releasing structure. The tail terminal portion, the second buckle structure and the releasing structure form a loop, the first buckle structure is capable of being engaged to the second buckle structure, and the first buckle structure moves in respect to the second buckle structure and the releasing structure. The first buckle structure and the magnetic attraction unit attract each other due to a magnetic attraction effect. By the loop design, merely one directional force is needed to achieve the objective of facilitating assembling and detaching, thus having results of reducing assembling cost and time consumption.

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

Abstract: A multiphoton absorption lithography processing system configured to process a to-be-processed object is provided. The multiphoton absorption lithography processing system includes a femtosecond laser source, a spatial light modulator, a lens array, and a stage. The femtosecond laser source is configured to emit a femtosecond laser beam. The spatial light modulator is configured to modulate the femtosecond laser beam into a modulated beam. The lens array is disposed on a path of the modulated beam and configured to divide the modulated beam into a plurality of sub-beams and make the sub-beams be focused on a plurality of position points at the to-be-processed object, so as to form multiphoton absorption reaction at the position points. The stage is configured to carry the to-be-processed object. The stage and the lens array are adapted to move with respect to each other in three dimensions.

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.