Patents by Inventor Chee Key Chung

Chee Key Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130769
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 28, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Chee-Key CHUNG
  • Patent number: 11315881
    Abstract: An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Chee-Key Chung
  • Patent number: 11289346
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Publication number: 20210320076
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, the arrangement of the bump body and the metal auxiliary layer allows complete reaction of the IMCs after reflowing the solder layer, and the volume of the conductive structures will not continue to shrink. As such, the problem of cracking of the conductive structures can be effectively averted.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 14, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20210296295
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
  • Publication number: 20210287962
    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.
    Type: Application
    Filed: May 12, 2020
    Publication date: September 16, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20210280530
    Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 9, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Chih-Hsun Hsu, Chee-Key Chung, Jia-Wei Pan, Chang-Fu Lin
  • Patent number: 11069661
    Abstract: An electronic package is formed by arranging two encapsulating portions of different materials between a plurality of electronic components stacked to each other to adjust a stress distribution of the electronic package, so that the degree of warpage of the electronic package can be optimally controlled.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 20, 2021
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Jhen Chen, Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11056470
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 6, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
  • Publication number: 20210082837
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: May 6, 2020
    Publication date: March 18, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Patent number: 10950520
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Publication number: 20210068260
    Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.
    Type: Application
    Filed: November 2, 2020
    Publication date: March 4, 2021
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20200402965
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: July 16, 2019
    Publication date: December 24, 2020
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
  • Patent number: 10863626
    Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20200335447
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 10763237
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 1, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Patent number: 10741500
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 11, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Publication number: 20200168523
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Application
    Filed: August 6, 2019
    Publication date: May 28, 2020
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Patent number: 10600708
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 24, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20200091109
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang