Patents by Inventor Chee Key Chung

Chee Key Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950520
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Publication number: 20210068260
    Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.
    Type: Application
    Filed: November 2, 2020
    Publication date: March 4, 2021
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20200402965
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: July 16, 2019
    Publication date: December 24, 2020
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
  • Patent number: 10863626
    Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20200335447
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 10763237
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 1, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Patent number: 10741500
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 11, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Publication number: 20200168523
    Abstract: An electronic package is provided. A heat dissipator is bonded via a thermal interface layer to an electronic component disposed on a carrier. The heat dissipator has a concave-convex structure to increase a heat-dissipating area of the thermal interface layer. Therefore, the heat dissipator has a better heat-dissipating effect.
    Type: Application
    Filed: August 6, 2019
    Publication date: May 28, 2020
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Wen-Shan Tsai, En-Li Lin, Kaun-I Cheng, Wei-Ping Wang
  • Patent number: 10600708
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 24, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20200091109
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Publication number: 20200043908
    Abstract: A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 6, 2020
    Inventors: Chee-Key Chung, Chang-Fu Lin, Han-Hung Chen, Jen-Chieh Hsiao, Rung-Jeng Lin, Kuo-Hua Yu, Hong-Da Chang
  • Patent number: 10522500
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Publication number: 20190252344
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Application
    Filed: May 15, 2018
    Publication date: August 15, 2019
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Publication number: 20190237374
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Application
    Filed: May 4, 2018
    Publication date: August 1, 2019
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 10361150
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20190181021
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Application
    Filed: April 4, 2018
    Publication date: June 13, 2019
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20190164861
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 30, 2019
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20190057917
    Abstract: An electronic package and a method of fabricating the same are provided. The method includes disposing an electronic component on a first side of an interposer, forming a first encapsulant on the first side of the interposer to encapsulate the electronic component, forming a plurality of conductive elements on a second side of the interposer, and forming a second encapsulant on the second side of the interposer to encapsulate the conductive elements. During thermal cycling of the electronic package, shrinkage forces of the first encapsulant and the second encapsulant can offset each other so as to mitigate warping of the interposer.
    Type: Application
    Filed: January 2, 2018
    Publication date: February 21, 2019
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Publication number: 20180269142
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Application
    Filed: May 9, 2017
    Publication date: September 20, 2018
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang