Patents by Inventor Chee-Wee Liu

Chee-Wee Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366916
    Abstract: A device includes a first semiconductor fin, a second semiconductor fin, first source/drain features, second source/drain features, a first gate structure, a second gate structure, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first semiconductor fin and the second semiconductor fin are adjacent to each other. The first source/drain features are on opposite sides of the first semiconductor fin. The second source/drain features are on opposite sides of the second semiconductor fin. The first gate structure is over the first semiconductor fin. The second gate structure is over the second semiconductor fin. The first VGAA transistor is over one of the first source/drain features. The second VGAA transistor is over one of the second source/drain features.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 25, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Yu YE, Chung-Yi LIN, Yun-Ju PAN, Chee-Wee LIU
  • Patent number: 11177430
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 16, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Publication number: 20210328012
    Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Publication number: 20210296112
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Patent number: 11043376
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 22, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Patent number: 11031470
    Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 8, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Patent number: 11018239
    Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.
    Type: Grant
    Filed: April 13, 2019
    Date of Patent: May 25, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Pin-Shiang Chen, Sheng-Ting Fan, Chee-Wee Liu
  • Publication number: 20210119047
    Abstract: The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsien TU, Chee-Wee LIU, Fang-Liang LU
  • Patent number: 10957784
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Publication number: 20210082482
    Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Publication number: 20210057408
    Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Hsiung HUANG, Chung-En TSAI, Chee-Wee LIU, Kun-Wa KUOK, Yi-Hsiu HSIAO
  • Publication number: 20210043538
    Abstract: A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.
    Type: Application
    Filed: October 9, 2020
    Publication date: February 11, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jhih-Yang YAN, Fang-Liang LU, Chee-Wee LIU
  • Publication number: 20200411328
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Yen-Ting CHEN, I-Hsieh WONG, Chee-Wee LIU
  • Publication number: 20200411671
    Abstract: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Fang-Liang LU, Pin-Shiang CHEN, Chee-Wee LIU
  • Patent number: 10879404
    Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 29, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
  • Publication number: 20200395530
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Patent number: 10867809
    Abstract: A method of forming a semiconductor device includes forming a doped region on a semiconductor substrate, in which the doped region comprises an impurity therein, and performing a laser anneal process to the doped region with a process gas containing a dopant gas, in which the dopant gas and the impurity comprise the same chemical element.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 15, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Ti Lu, Meng-Chin Lee, Fang-Liang Lu, Chee-Wee Liu
  • Publication number: 20200373334
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee Wee Liu
  • Publication number: 20200328287
    Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.
    Type: Application
    Filed: April 13, 2019
    Publication date: October 15, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Pin-Shiang CHEN, Sheng-Ting FAN, Chee-Wee LIU
  • Patent number: 10804180
    Abstract: A device includes a non-insulator structure, a first ILD layer, a first thermal via, and a first electrical via. The first ILD is over the non-insulator structure. The first thermal via is through the first ILD layer and in contact with the non-insulator structure. The first electrical via is through the first ILD layer and in contact with the non-insulator structure. The first thermal via and the first electrical via have different materials and the same height.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 13, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jhih-Yang Yan, Fang-Liang Lu, Chee-Wee Liu