Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: A power delivery system and a method for setting the parameters of the power delivery system. The effective resistance of the capacitors for each stage may be set to be substantially equal to the effective resistance of the previous stage, and the time capacitive constant of the capacitors may be set to be substantially equal to the effective inductive time constant of the previous stage.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A method and system are disclosed for processing data from a computer network to determine an occurrence of and characterize a particular activity associated with the computer network. In accordance with exemplary embodiments of the present invention, a collection of data is managed that corresponds to events associated with the computer network. At least one model is established to correlate an occurrence of a predetermined set of events. At least one hypothesis is formed, using the at least one model, that characterizes the particular activity associated with the computer network. The at least one hypothesis is evaluated using the at least one model. The steps of forming and evaluating are performed interactively with the step of managing to iteratively update the collection of data.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A method for fabricating a socket (300, FIG. 3) includes fabricating a conductive structure (310, FIG. 3) and embedding the conductive structure in a housing (302). The housing includes multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). In one embodiment, the embedded conductive structure (310) is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4).

Abstract: A method for determining the location of a mobile unit (MU) in a wireless communication system and presenting it to a remote party. The location of a remote MU is determined by comparing a snapshot of a predefined portion of the radio-frequency (RF) spectrum taken by the MU to a reference database containing multiple snapshots taken at various locations. The result of the comparison is used to determine if the MU is at a specific location. The comparison may be made in the MU, or at some other location situated remotely from the MU. In the latter case, sufficient information regarding the captured fingerprint is transmitted from the MU to the remote location. The database may be pre-compiled or generated on-line.

Abstract: A method for determining the location of a mobile unit (MU) in a wireless communication system and presenting it to a remote party. The location of a remote MU is determined by comparing a snapshot of a predefined portion of the radio-frequency (RF) spectrum taken by the MU to a reference database containing multiple snapshots taken at various locations. The result of the comparison is used to determine if the MU is at a specific location. The comparison may be made in the MU, or at some other location situated remotely from the MU. In the latter case, sufficient information regarding the captured fingerprint is transmitted from the MU to the remote location. The database may be pre-compiled or generated on-line.

Abstract: A method for determining the location of a mobile unit (MU) in a wireless communication system and presenting it to a remote party. The location of a remote MU is determined by comparing a snapshot of a predefined portion of the radio-frequency (RF) spectrum taken by the MU to a reference database containing multiple snapshots taken at various locations. The result of the comparison is used to determine if the MU is at a specific location. The comparison may be made in the MU, or at some other location situated remotely from the MU. In the latter case, sufficient information regarding the captured fingerprint is transmitted from the MU to the remote location. The database may be pre-compiled or generated on-line.

Abstract: An apparatus is disclosed. The apparatus has a printed circuit board and one or several integrated circuit substrates mounted to the printed circuit board. At least one SMT component with two or more terminals is arranged between the printed circuit board and the package. In one embodiment, the SMT component replaces interconnects in the ball grid array used to mount the substrate to the printed circuit board while simultaneously connecting the SMT terminals to the substrate and the printed circuit board. The disclosed apparatus of SMT components mount results in significant reduction of inductance of the SMT connection to the substrate.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Abstract: An electronic assembly includes multiple discrete capacitors (504, FIG. 5), which are surface mounted to or embedded within an electronic housing, such as an integrated circuit package (1504, FIG. 15). One or more side terminals (510) of adjacent capacitors are electrically connected through lateral connections (512, 620, FIGS. 5, 6). These lateral connections provide an extremely low lateral inductance current path between the discrete capacitors.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.