Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.

Abstract: An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.

Abstract: A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.

Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.

Abstract: A semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure wrapping around the first semiconductor channel layer, and first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure wrapping around the second semiconductor channel layer, and second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure wraps around the first semiconductor channel layer.

Abstract: A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

Abstract: A semiconductor device includes a substrate having a semiconductor fin, a first transistor over the substrate, and a second transistor vertically above the first transistor. The first transistor includes a first gate structure over the semiconductor fin, in which in a cross-sectional view, the semiconductor fin comprises a channel portion in contact with a bottom surface of the first gate structure, and source/drain portions on opposite sidewalls of the first gate structure. The second transistor includes a semiconductor channel layer above the semiconductor fin, a second gate structure over the semiconductor channel layer, and source/drain epitaxy structures on opposite ends of the semiconductor channel layer.

Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate, a plurality of inner spacer features interleaving the plurality of nanostructures. The plurality of nanostructures are arranged along a direction perpendicular to the substrate. The plurality of inner spacer features include a bottommost inner spacer feature and upper inner spacer features disposed above the bottommost inner spacer feature. The first height of the bottommost inner spacer feature along the direction is greater than a second height of each of the upper inner spacer features.

Abstract: A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

Abstract: A method for manufacturing an integrated circuit device is provided. The method includes depositing a dielectric layer over a substrate; depositing a first gate electrode layer over the dielectric layer; removing a first portion of the dielectric layer to leave an opening between the first gate electrode layer, the substrate, and second portions of the dielectric layer; depositing a first gate dielectric layer, such that the first gate dielectric layer has a first portion in the opening and a second portion over a top surface of the first gate electrode layer; and depositing a semiconductor layer, such that the semiconductor layer has a first portion in the opening and a second portion over a top surface of the first gate dielectric layer.

Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

Abstract: A gate all-around field effect transistor includes a substrate, a first sacrificial layer, a channel layer, a protective layer, a composite field oxide layer, a drain electrode, a source electrode and a gate stack layer. The first sacrificial layer is disposed on the substrate. The channel layer is disposed on the first sacrificial layer, and extends from a drain region to a source region. The protective layer is disposed on the channel layer in the drain and source regions. The composite field oxide layer is disposed on the protective layer in the drain and source regions, and has a drain opening and a source opening for exposing the protective layer. The drain and source electrodes are respectively disposed in the drain and source openings, and in electrical contact with the protective layer. The gate stack layer is disposed on the substrate in the channel region.

Abstract: A method for manufacturing a split double gate transistor includes: forming a first fin on a substrate; removing sacrificial layers from a portion of the first fin; sequentially forming a first gate insulating layer, a channel layer and a protection layer on exposed portions of each gate metal layer; performing a patterning process to form a second fin; patterning the second fin to form a plurality of first recesses and a plurality of second recesses; forming a plurality of inner spacer layers; forming a first gate component, a drain component and a source component; removing the protection layer; and sequentially forming a second gate insulating layer, a plurality of gate connectors, and a second gate component.

Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.

Abstract: A method includes forming a first bottom-tier pull-up transistor and a second bottom-tier pull-up transistor over a substrate, wherein the first and second bottom-tier pull-up transistors are comprised in a static random access memory (SRAM) cell; forming a first middle-tier pull-down transistor and a second middle-tier pull-down transistor over the first and second bottom-tier pull-up transistors, wherein the first and second middle-tier pull-down transistors are comprised in the SRAM cell; forming a first top-tier pass-gate transistor, a second top-tier pass-gate transistor, a third top-tier pass-gate transistor, and a fourth top-tier pass-gate transistor over the first and second middle-tier pull-down transistors, wherein the first, second, third, and fourth top-tier pass-gate transistors are comprised in the SRAM cell.

Abstract: A method includes forming a first read pull-down transistor and a first read pass-gate transistor over a substrate at a first level height, wherein the first read pull-down and first read pass-gate transistors are of a first read port of a static random access memory (SRAM) cell; forming a second read pull-down transistor and a second read pass-gate transistor over the substrate at a second level height higher than the first level height, wherein the second read pull-down and second read pass-gate transistors are of a second read port of the SRAM cell.

Abstract: A method for fabricating an integrated circuit structure is provided. The method include forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device comprises a gate structure and first and second source/drain regions respectively on opposite sides of the gate structure; forming a frontside interconnect structure over a frontside of the semiconductor device, wherein the frontside interconnect structure comprise a frontside metal line and a frontside dielectric layer, and the frontside metal line is electrically connected to the first source/drain region of the semiconductor device; depositing a high-k dielectric layer over a backside of the semiconductor device, wherein a dielectric constant of the high-k dielectric layer is greater than about 3.9; etching an opening in the high-k dielectric layer to expose a backside of the second source/drain region; and forming a backside metal feature in the opening in the high-k dielectric layer.