Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, an underlayer, a ferroelectric material layer, and a conductive layer. The underlayer covers the semiconductor substrate. The ferroelectric material layer covers the underlayer, in which the underlayer has a surface facing the ferroelectric material layer, and the surface has a root mean square roughness of less than 1 nm. The conductive layer covers the ferroelectric material layer.

Abstract: An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A method includes forming a stack of alternating oxide semiconductor channel layers and sacrificial layers over a substrate; removing first portions of the sacrificial layers to expose channel regions of the oxide semiconductor channel layers; forming a gate structure wrapping around each of the channel regions of the oxide semiconductor channel layers; removing second portions of the sacrificial layers to expose source/drain regions of the oxide semiconductor channel layers; and forming source/drain electrodes wrapping around and in contact with each of the source/drain regions of the oxide semiconductor channel layers, wherein the source/drain electrodes are made of a metal-containing material.

Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

Abstract: A semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure wrapping around the first semiconductor channel layer, and first source/drain epitaxy structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure wrapping around the second semiconductor channel layer, and second source/drain epitaxy structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure wraps around the first semiconductor channel layer.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A non-volatile memory cell includes a capacitor which includes a top electrode, a bottom electrode, a ferroelectric layer disposed between the top electrode and the bottom electrode, and an amorphous layer disposed between the top electrode and the bottom electrode, wherein an atomic arrangement of the amorphous layer is different from an atomic arrangement of the top electrode and the bottom electrode. A method of fabricating a non-volatile memory cell and a memory cell array thereof are also disclosed.

Abstract: A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Abstract: A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.

Abstract: A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Abstract: A device includes a substrate, a semiconductor layer and a ferroelectric layer. The semiconductor layer is over the substrate. The semiconductor layer is a single crystal silicon layer or a single crystal germanium layer. The ferroelectric layer is over the semiconductor layer. The ferroelectric layer is in physical contact with the semiconductor layer and has an orthorhombic phase.

Abstract: An integrated circuit device includes a semiconductor layer, an oxide semiconductor layer, and a gate structure. The semiconductor layer is free of oxygen. The oxide semiconductor layer is over and spaced apart from the semiconductor layer. The gate structure wraps around a channel region of the semiconductor layer and a channel region of the oxide semiconductor layer.