Patents by Inventor Chen-Chiu Hsue
Chen-Chiu Hsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11362099Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.Type: GrantFiled: May 8, 2020Date of Patent: June 14, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ching-Hua Chen, Bing-Chen Ji, Shun-Tsung Yu, Ming-Yuan Lin, Han-Chao Lai, Jih-Wen Chou, Chen-Chiu Hsue
-
Publication number: 20210351274Abstract: A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.Type: ApplicationFiled: July 12, 2020Publication date: November 11, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chen-Chiu Hsue, Hsun-Kuei Chan, Kai-An Hsueh, Ming-Te Huang, Li-Tsen Jiang, Hung-Kwei Liao
-
Patent number: 11171217Abstract: A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.Type: GrantFiled: July 12, 2020Date of Patent: November 9, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Chen-Chiu Hsue, Hsun-Kuei Chan, Kai-An Hsueh, Ming-Te Huang, Li-Tsen Jiang, Hung-Kwei Liao
-
Publication number: 20210265368Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.Type: ApplicationFiled: May 8, 2020Publication date: August 26, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ching-Hua Chen, Bing-Chen Ji, Shun-Tsung Yu, Ming-Yuan Lin, Han-Chao Lai, Jih-Wen Chou, Chen-Chiu Hsue
-
Patent number: 7411276Abstract: A photosensitive device having at least an insulator layer including a plurality of photoreceiving regions disposed on a substrate. A plurality of conductive patterns is disposed on the insulator layer without covering the photoreceiving regions. A flattened dielectric layer is disposed on the conductive patterns and the insulator layer, wherein a surface of the dielectric layer is higher than a surface of the conductive patterns in a range between 2000 ? to 4000 ?.Type: GrantFiled: September 1, 2006Date of Patent: August 12, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Ming-Jeng Huang, Chen-Chiu Hsue
-
Patent number: 7183606Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.Type: GrantFiled: July 7, 2005Date of Patent: February 27, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Leo Wang, Chien-Chih Du, Da Sung, Chen-Chiu Hsue
-
Publication number: 20070004075Abstract: A photosensitive structure and method of fabricating the same. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP.Type: ApplicationFiled: September 1, 2006Publication date: January 4, 2007Inventors: Ming-Jeng Huang, Chen-Chiu Hsue
-
Patent number: 7125738Abstract: A method of fabrication of a photosensitive device is disclosed. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP thereof. The dielectric layer comprises a first dielectric layer formed by PECVD and a second dielectric layer formed by HDPCVD.Type: GrantFiled: October 14, 2004Date of Patent: October 24, 2006Assignee: Powerchip Semiconductor Corp.Inventors: Ming-Jeng Huang, Chen-Chiu Hsue
-
Publication number: 20060154418Abstract: A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.Type: ApplicationFiled: June 13, 2005Publication date: July 13, 2006Inventors: Ko-Hsing Chang, Tung-Po Chen, Tung-Ming Lai, Chen-Chiu Hsue
-
Patent number: 7074674Abstract: A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.Type: GrantFiled: June 13, 2005Date of Patent: July 11, 2006Assignee: Powerchip Semiconductor Corp.Inventors: Ko-Hsing Chang, Tung-Po Chen, Tung-Ming Lai, Chen-Chiu Hsue
-
Publication number: 20060084194Abstract: A photosensitive structure and method of fabricating the same. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP.Type: ApplicationFiled: October 14, 2004Publication date: April 20, 2006Inventors: Ming-Jeng Huang, Chen-Chiu Hsue
-
Publication number: 20050255658Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.Type: ApplicationFiled: July 7, 2005Publication date: November 17, 2005Inventors: Leo Wang, Chien-Chih Du, Da Sung, Chen-Chiu Hsue
-
Patent number: 6953963Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.Type: GrantFiled: January 8, 2004Date of Patent: October 11, 2005Assignee: Powerchip Semiconductor Corp.Inventors: Leo Wang, Chien-Chih Du, Da Sung, Chen-Chiu Hsue
-
Publication number: 20050051833Abstract: A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region.Type: ApplicationFiled: January 8, 2004Publication date: March 10, 2005Inventors: Leo Wang, Chien-Chih Du, Da Sung, Chen-Chiu Hsue
-
Patent number: 6696222Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.Type: GrantFiled: July 24, 2001Date of Patent: February 24, 2004Assignee: Silicon Integrated Systems Corp.Inventors: Chen-Chiu Hsue, Shyh-Dar Lee
-
Publication number: 20030228750Abstract: A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO2, NH3, NO2, SiH4, trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.Type: ApplicationFiled: June 7, 2002Publication date: December 11, 2003Inventors: Shyh-Dar Lee, Chen-Chiu Hsue
-
Patent number: 6649512Abstract: A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO2, NH3, NO2, SiH4, trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.Type: GrantFiled: June 7, 2002Date of Patent: November 18, 2003Assignee: Silicon Integrated Systems Corp.Inventors: Shyh-Dar Lee, Chen-Chiu Hsue
-
Patent number: 6603167Abstract: A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.Type: GrantFiled: March 11, 2002Date of Patent: August 5, 2003Assignee: Silicon Integrated Systems Corp.Inventors: Chen-Chiu Hsue, Shyh-Dar Lee
-
Publication number: 20030141605Abstract: A method of forming an identifying mark on a semiconductor wafer. The identifying mark, for example a bar code or a character of patterns or words, is formed on the side wall of the semiconductor wafer to avoid contamination and the creation of failure dies during the formation of the identifying mark.Type: ApplicationFiled: July 9, 2002Publication date: July 31, 2003Applicant: Silicon Integrated Systems Corp.Inventors: Shyh-Dar Lee, Chen-Chiu Hsue
-
Publication number: 20030116826Abstract: An interconnect structure has at least two adjacent metal wiring lines patterned on a semiconductor substrate and separated by a gap. A dielectric layer is formed on the metal wiring lines to fill the gap to a predetermined thickness. A metallic barrier layer, which may be of Ti, TiN, Ta, TaN, Cu or copper alloys are sandwiched between the sidewall of the metal wiring line and the dielectric layer. In addition, a contact plug passing through the dielectric layer is electrically connected to the top of the metal wiring line.Type: ApplicationFiled: December 20, 2001Publication date: June 26, 2003Inventors: Chen-Chiu Hsue, Shyh-Dar Lee, Tzu-Kun Ku