Abstract: The present invention provides a method to fabricate a interconnect structure. First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench. And a barrier layer is formed to on the trench. Afterwards, a metal layer is formed to fill into the trench over the barrier layer. Then a chemical mechanical polishing (CMP) process is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. After the CMP process, a reduction process is performed by providing a reduction gas to remove the metal oxide generated on the metal layer. Finally, a sealing layer is formed to cover the metal layer and the inter-metal dielectric layer.

Abstract: A method and a structure of interconnects with dual dielectric spacers is disclosed. A substrate with a plurality of interconnects is provided. A first dielectric layer is formed on the interconnects and the substrate. The first dielectric layer is partially etched back to expose a partial surface of the substrate and the top surface of the interconnects, leaving remaining first dielectric layers on the sides of the interconnects as first spacers. A second dielectric layer is formed on the interconnects, the first spacers and the substrate. The second dielectric layer is partially etched back to expose a partial surface of the substrate and the top surface of the interconnects, leaving remaining first spacers on the surface of the first spacers as second spacers. A third dielectric layer is formed on the substrate, the second spacers and the interconnects. Thus, the first spacers serve as stress buffer layers and the second spacers serve as etching stop layers and/or supporting layers of the interconnects.

Abstract: A method and a structure of interconnects with dielectric spacers is disclosed. A semiconductor substrate with a plurality of interconnects is provided. A conformal first dielectric layer is formed on the interconnects and the substrate. The first dielectric layer is partially etched back to expose a partial surface of the substrate and the top surface of the interconnects, leaving remaining first dielectric layers on the sides of the interconnects, wherein the remaining first dielectric layers are spacers. A second dielectric layer is formed on the substrate, the spacers and the interconnects, and planarization is performed on the second dielectric layer. Thus, the spacers serve as etching stop layers and/or supporting layers of the interconnects.

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract: The present invention discloses an electrostatic effect free mask. The mask is made by depositing a layer of slightly conductive and transparent polymer onto a mask. The present invention can prevent adjacent patterns from point to point discharging during processes, and thus maintain the integrity of the mask.

Abstract: A method for forming a metal capacitor in a damascene process is provided. Before the metal capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. The stacked layers are then subjected to a masking process and an etching process to form the thin-film capacitor and the metal wire with the remaining insulator and the remaining second metal layer thereon. The remaining second metal layer located on the metal wire is removed by another masking process and another etching process. After forming the capacitor and the metal wire, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: This invention provides a method for forming a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: The present invention provides a method for fabricating a metal capacitor. A first level metal layer is formed on a substrate. Then, the first level metal layer is patterned to concurrently form a first metal line and a second metal line. The second metal line defines a metal capacitor region and is used as a lower electrode of the metal capacitor. Then, an insulating layer is conformably formed on the substrate, the first metal line, and the second metal line. A first intermetal dielectric layer is formed on the insulating layer. Then, the first intermetal dielectric layer is subjected to planarization treatment such that the planarization treatment finally exposes the insulating layer. Finally, a third metal line is formed on the insulating layer in the metal capacitor region such that the third metal line is used as the upper electrode of the metal capacitor.

Abstract: This invention provides a method for forming a metal capacitor with a damascene process. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by the following steps. An opening for a capacitor is formed in a second insulator. Then, a first metal layer, a dielectric layer and a second metal layer are conformally formed in the opening on the second insulator. The stacked layers are subjected to a chemical mechanical polishing process until the second insulator is exposed. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A DRAM capacitor is formed having a crown structure with a reduced number of processing steps. A planarized insulating layer is provided over the DRAM cell's transfer FET and a contact via is opened to one of the source/drain regions of the transfer FET. A layer of polysilicon is deposited to fill the contact via and to extend over the surface of the insulating layer, providing a thick polysilicon layer on the insulating layer. Conventional photolithography is used to define a first etching mask with an element on the thick polysilicon aligned over the contact via. The polysilicon layer is etched partially through using the first etching mask and the photoresist mask is removed. A layer of oxide is deposited over the elevated and recessed surfaces of the polysilicon layer and an etch back process is performed to form a second etching mask consisting of oxide spacer structures along the edges of the elevated portion of the polysilicon layer.

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. A dielectric layer is deposited over the metal lines and dummy metal areas wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. The dummy metal areas are also etched into island pieces with size similar to the feature size. Narrow trenches with the same constant width and depth surround the dummy metal islands. A dielectric layer is deposited over the metal lines and dummy metal islands wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

Abstract: SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage of between 5.times.10.sup.12 to 2.times.10.sup.13 /cm.sup.2 at an energy of 200-1000 KeV. Use of a P-type substrate having a blanket N-well region formed by ion implantation are less expensive than the N-type substrates conventionally used, and make the SRAM processing techniques compatible with the P-type substrates conventionally used in microprocessors and other logic devices.

Abstract: A process for fabricating an improved planar field oxide (FOX) structure on a silicon substrate was achieved. The process involves forming recessed areas in the silicon substrate where the field oxide is require. A thin silicon oxide is formed on the surface of the recessed areas as a nucleation layer and then a thicker silicon oxide layer is selectively deposited in the recess areas by Liquid Phase Deposition (LPD). The planar FOX structure formed by LPD can be used in conjunction with a FOX structure formed by the conventional LOCal Oxidation of Silicon (LOCOS) process on the same substrate. The planar field oxide formed by LPD eliminates the bird beak structure and the lateral diffusion of the channel stop implant commonly associated with the LOCOS structure.

Abstract: A furnace with a large quartz tube with a gas inlet on one end, and a large opening at the other end for introducing and withdrawn wafers on a support. At least one small quartz tube is provided within and adjacent the sidewall of the large tube that has a gas inlet on one end outside of the large tube, and apertures in the sidewall. In use, a major stream of gas is provided by a gas inlet on the large tube that flows longitudinally through the large tube. A series of secondary streams of gas are provided from the apertures in the small tube that flow perpendicular to the major stream and across the surfaces of the wafers.

Abstract: A method of manufacture for flat-cell Mask ROM devices on a silicon semiconductor substrate covered with a first gate oxide layer comprises, forming a first conductor structure on the first gate oxide layer, forming a buried conductive structure within the substrate by ion implantation with a portion thereof in juxtaposition with the first conductor structure, etching away the exposed surfaces of the first gate oxide layer exposing portions of the semiconductor, forming a second gate oxide layer on the surface of the semiconductor, and forming a second conductor structure on the second gate oxide layer.