Abstract: A method of fabricating an IMD layer is provided on a semiconductor substrate, on which at least two adjacent metal wiring lines separated by a gap are patterned. A first dielectric layer, preferably of silicon oxide, is formed on the metal wiring lines to partially fill the gap below the level of the top of the metal wiring lines using high density plasma chemical vapor deposition (HDPCVD). Then, a second dielectric layer, preferably of silicon oxide, is formed on the first dielectric layer to completely fill the gap to a predetermined thickness using PECVD. Thus, the first dielectric layer and the second dielectric layer between the two adjacent metal wiring lines serve as the IMD layer.

Abstract: An interconnect structure comprises a first level metal wiring line patterned on a semiconductor substrate, an inter-metal dielectric (IMD) layer formed on the metal wiring line, a contact plug passing through the IMD layer and electrically connected to the top of the first level metal wiring line, and a second level metal wiring line patterned on the IMD layer and electrically connected to the top of the contact plug. A cap layer is sandwiched between the top of the IMD layer and the bottom of the second level metal wiring line.

Abstract: A process for preparing a porous low dielectric constant material. The process mainly uses critical point drying technique. By changing the pressure and temperature, a liquid component is released from a specific wet film composition. Thus, a porous low dielectric constant material is obtained.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, using photolithography and etching, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. The diameter of the first opening is larger then the second opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed to reach a predetermined depth. Thereby, a trench is formed over the via hole.

Abstract: A metallic interconnect structure has at least a metallic interconnects patterned on a semiconductor substrate, and at least a metallic spacer formed on the sidewall of the metallic interconnect. The metallic interconnect is Al, Cu or Al—Si—Cu. The first metallic layer is Ti, TiN, Ta, or TaN.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: A method for fabricating a polysilicon capacitor. The method includes the following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to concurrently form a first polysilicon line and a second polysilicon line. The second polysilicon line defines a polysilicon capacitor region and is used as a lower electrode of the polysilicon capacitor. Next, an insulating layer is formed conformably on the substrate, the first polysilicon line, and the second polysilicon line. A first dielectric layer is formed on the insulating layer, which is then subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. Finally, a third polysilicon line is formed on the insulating layer in the polysilicon capacitor region such that the third polysilicon line is used as an upper electrode of the polysilicon capacitor.

Abstract: A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire.

Abstract: A method for manufacturing a MOS device with improved well control stability. The method includes the steps of providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.

Abstract: A method to fabricate an interconnect structure is provided. First, an inter-metal dielectric layer is formed on a substrate. Then the inter-metal dielectric layer is etched to form a trench, and a barrier layer is formed on the trench. After, a metal layer is formed to fill in the trench over the barrier layer. Then a chemical mechanical polishing (CMP) process is performed to remove the barrier layer and the metal layer on the inter-metal dielectric layer. Finally, a conductive sealing layer is formed to cover the metal layer.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: This invention provides a method for forming a metal capacitor in a damascene process. Before the thin-film capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene process. The lower electrode is formed in a dual damascene process, which is also used to form the dual damascene structures comprising wires and plugs. An insulator is disposed to isolate the dual damascene structures with each other. In this dual damascene process, an anti-reflection layer is used and formed on the insulator, and the anti-reflection layer is also used as a hard mask layer, a polishing stop layer and an etching stop layer. Then, another insulator and a metal layer are formed on the anti-reflection layer, and encounter a photolithography step and an etching step to obtain an upper electrode and a capacitor insulator. After forming the metal capacitor, the upper interconnections are fabricated with another dual damascene processes.

Abstract: A method for fabricating a polysilicon capacitor. The method includes the following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to concurrently form a first polysilicon line and a second polysilicon line. The second polysilicon line defines a polysilicon capacitor region and is used as a lower electrode of the polysilicon capacitor. Next, an insulating layer is formed conformably on the substrate, the first polysilicon line, and the second polysilicon line. A first dielectric layer is formed on the insulating layer, which is then subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. Finally, a third polysilicon line is formed on the insulating layer in the polysilicon capacitor region such that the third polysilicon line is used as an upper electrode of the polysilicon capacitor.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: This invention provides a method for forming a metal capacitor in a damascene process. Before the thin-film capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene process. The lower electrode is formed in a dual damascene process, which is also used to form the dual damascene structures comprising wires and plugs. An insulator is disposed to isolate the dual damascene structures with each other. In this dual damascene process, an anti-reflection layer is used and formed on the insulator, and the anti-reflection layer is also used as a hard mask layer, a polishing stop layer and an etching stop layer. Then, another insulator and a metal layer are formed on the anti-reflection layer, and encounter a photolithography step and an etching step to obtain an upper electrode and a capacitor insulator. After forming the metal capacitor, the upper interconnections are fabricated with another dual damascene processes.