Abstract: A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide.

Abstract: A semiconductor ESD device on a substrate is covered with SiO.sub.2 and FOX regions, made by forming a blanket first gate layer on the device including the SiO.sub.

Abstract: A method of manufacture for flat-cell Mask ROM devices on a silicon semiconductor substrate covered with a first gate oxide layer comprises, forming a first conductor structure on the first gate oxide layer, forming a buried conductive structure within the substrate by ion implantation with a portion thereof in juxtaposition with the first conductor structure, etching away the exposed surfaces of the first gate oxide layer exposing portions of the semiconductor, forming a second gate oxide layer on the surface of the semiconductor, and forming a second conductor structure on the second gate oxide layer.

Abstract: A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.

Abstract: A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric.

Abstract: A semiconductor ROM device on a semiconductor substrate includes an array of parallel bit lines oriented in a first direction. A blanket word line layer formed on the device is covered with a word line mask with word line patterns orthogonal to the bit lines used during etching of word line layer to form word lines. A blanket glass layer is formed over the device and then covered with a patterned negative negative code implant mask. A silicon dioxide layer is formed on the blanket glass layer around the patterned negative negative code implant mask. The negative negative code implant mask is removed leaving a ROM code opening through the silicon dioxide layer, whereby the silicon dioxide layer forms a ROM code implant mask. The ROM code opening is centered on a word line conductor, and a code ion implant of dopant is made through the ROM code opening forming a code implant doped region in the substrate below the word line. The silicon dioxide layer is formed by liquid phase deposition.

Abstract: A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.

Abstract: A ROM device with an array of cells and a method of manufacturing comprises: forming closely spaced conductors in the surface of a semiconductor substrate having a second type of background impurity. Insulation is formed on the substrate. Closely spaced, parallel, conductors on the insulation are arranged orthogonally to the line regions. Glass insulation is formed over the conductors. Reflowing the glass insulation, forming contacts and forming a metal layer on the glass insulation follow. A resist is formed, exposed forming a resist metal pattern, then etching through the resist to pattern metal and removing the resist. Depositing a resist onto the patterned metal, and exposing the second resist with a custom code pattern, developing the resist into a mask follow. Impurity ions are implanted into the substrate adjacent to the conductors through the openings in a second resist layer.

Abstract: A method and structure for manufacturing a self-aligned contact, for connecting conductive lines to active regions in a silicon substrate, is described. There is a first insulating layer over the silicon substrate, with openings over the active regions. A barrier metal layer is formed over the active regions, along surfaces of the openings, and over a portion of the horizontal surfaces of the first insulating layer in the region adjacent to the openings. There is a refractory metal layer over the barrier metal layer. Conductive lines are self-aligned over the barrier metal layer and over the refractory metal layer. Sidewall spacers are formed adjacent to the conductive lines and over those regions of the refractory metal layer not covered by the conductive lines.

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract: A method for fabricating a capacitors on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a field effect transistor (FET), having one capacitor aligned over and contacting the source/drain of the FET in the device region. The capacitor is increased in capacitance by forming a double recess in the bottom electrodes of the storage capacitors. The method of forming the double recess utilizes a sidewall spacer and local oxidation technique. After forming the bottom electrode having the double recess an insulating layer having a high dielectric constant is deposited as the inter-electrode insulator and a stop electrode is formed, completing the storage capacitor and the dynamic random access memory (DRAM) storage cell.

Abstract: A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. Theis reduces bit line sheet resistance and increases the punch through voltage between adjacent bit lines.

Abstract: A semiconductor device manufactured by the process including a semiconductor substrate, which comprises the steps of forming buried bit lines below the surface of said semiconductor substrate forming an individual source and drain regions; forming a gate oxide layer on the surface of the substrate; forming a first conductive structure on the gate oxide layer; forming an insulating structure in contact with the first conductive structure; removing material from the surface of the first conductive structure to expose at least a portion of the surface beneath the first conductive structure; and forming on the remaining structure on the semiconductor substrate metal line structures having edges vertically aligned with and above the source and drain regions in the buried bit lines; whereby a compound conductive structure is provided on the semiconductor substrate.

Abstract: A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.

Abstract: A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.

Abstract: A method of forming an ESD protection device simultaneously with an integrated circuit which includes FET devices is described. A silicon substrate on which there are field oxide regions, gates, and active regions is provided. A first ion implant in a vertical direction is performed of a conductivity-imparting dopant, into the active regions of the ESD protection device and the FET devices. An insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. The spacers are removed from the gate of the ESD protection device. A second ion implant in a vertical direction is performed of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant, into active regions of both the ESD protection device and the FET devices.

Abstract: A new stacked capacitor structure having increased capacitance and a method of fabrication was accomplished. The capacitor stores data in the form of stored charge and together with a field effect transistor (MOSFET) make up the individual Dynamic Random Access Memory (DRAM) storage cells on a DRAM chip. The improved capacitor is fabricated using an electrically conducting layer in the bottom electrode of the capacitor, which is substantially different in composition from silicon. The conducting layer preferably being a refractory metal or a refactory metal silicides, such as, tungsten (W) or tungsten silicide (WSi). The bottom electrode is formed from a multilayer composed of a thin polysilicon layer, the conducting layer and an upper thicker polysilicon layer. Vertical capacitor sidewalls are formed from the upper polysilicon layer by photoresist masking and then etching to the conducting layer. The conducting layer provides an etch end point for accurately etching to the correct depth without over etching.

Abstract: In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

Abstract: A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth.

Abstract: A method for fabricating an array of closely spaced storage capacitors, with increased capacitance, on a dynamic random access memory (DRAM) chip is achieved. The capacitors are increased in capacitance by minimizing the spacings between the adjacent bottom electrodes of the storage capacitors and, thereby increases the area of the capacitor electrodes. A local oxidation techniques is used to form a silicon oxide etch mask, on the bottom electrode polysilicon layer, that extends laterally under a patterned silicon nitride masking layer. This encroachment of the silicon oxide under the patterned silicon nitride layer reduces the spacing between electrodes, exceeding the resolution limits of the photoresist. The silicon nitride is removed and the silicon oxide mask is used to pattern the polysilicon layer forming an array of closely spaced polysilicon bottom electrodes. The silicon oxide is removed and an inter-electrode dielectric is deposited on the array of bottom electrode.