Abstract: A local learning system in a local artificial intelligence (AI) device includes at least one data source, a data collector, a training data generator, and a local leaning engine. The data collector is connected to the at least one data source, and used to collect training data. The training data generator is connected to the data collector, and used to analyze the training data to produce paired examples for supervised learning, or unlabeled data for unsupervised learning. The local leaning engine is connected to the training data generator, and includes a local neural network. The local neural network is trained by the paired examples or the unlabeled data in a training phase, and makes inference in an inference phase.

Abstract: A spread spectrum based audio frequency communication system at least includes a transmitting apparatus. The transmitting apparatus includes a first dot-product module, a summation module, a transmitting modulation module, a mixture module, a digital-to-analog converter, and a transmitter. The first dot-product module is configured to perform a dot-product of a first data and a first pseudo-noise code, and derive a first spreading data. The summation module is configured to sum up the first spreading data and a second spreading data to form a summed data. The transmitting modulation module is configured to vary a carrier signal with the summed data to form a modulated signal. The mixture module is configured to mix the modulated signal and an acoustic signal up to form a mixed signal. The digital-to-analog converter is configured to convert the mixed signal into acoustic waves. The transmitter transmits the acoustic waves.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

Abstract: An impact resistant structure adapted to an electronic component. The impact resistant structure includes a resistance stack layer and a damping laminate. The resistance stack layer is disposed on a first surface of the electronic component, and the damping laminate is disposed on a second surface of the electronic component. The second surface of the electronic component is opposite to the first surface. The damping laminate includes a soft film and a support film, where the support film is disposed between the soft film and the electronic component.

Abstract: A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer with a hole over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer and forming a first mask element with a trench opening over the second dielectric layer. The method further includes forming a second mask element over the first mask element, and the second mask element has a via opening. In addition, the method includes etching the second dielectric layer through the via opening and etching the second dielectric layer through the trench opening. As a result, a trench and a via hole are formed in the second dielectric layer and the first dielectric layer, respectively. The method includes forming a conductive material in the via hole and the trench.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphehe layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

Abstract: A method for matrix by vector multiplication, applied in an artificial neural network system, is disclosed. The method comprises: compressing a plurality of weight values in a weight matrix and indices of an input vector into a compressed main stream; storing M sets of synapse values in M memory devices; and, performing reading and MAC operations according to the M sets of synapse values and the compressed main stream to obtain a number M of output vectors. The step of compressing comprises: dividing the weight matrix into a plurality of N×L blocks; converting entries of a target block and corresponding indices of the input vector into a working block and an index matrix; removing zero entries in the working block; shifting non-zero entries row-by-row to one of their left and right sides in the working block; and, respectively shifting corresponding entries in the index matrix.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.

Abstract: A device is for removing a first substrate from a second substrate or adhering the first substrate to the second substrate. The device includes a carrier, a flexible member and a supporting member. The carrier is for fixing the first substrate. The flexible member is for fixing the second substrate. The supporting member is connected to the carrier and the flexible member. The carrier and the flexible member are spaced a distance from each other. The carrier, the flexible member and the supporting member together define a first variable pressure chamber. The first variable pressure chamber has a first air hole.

Abstract: A glass-mounted image, proof against the effects of oxidation, which can be viewed with different effects from the front or from the rear includes a transparent base and a pattern layer. The transparent base includes a front surface and a rear surface and the pattern layer is formed on the rear surface. The pattern layer is formed by inkjet printing UV-curable ink and curing the ink and the pattern layer is a fogged surface in contrast with the opposing smooth and polished appearance seen through the glass from the other side.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of connecting even or odd numbered lines that are in the x-direction of a 1-D patterning layout through 2-D interconnects in the y-direction. Depending on device design needs, 2-D interconnects may be perpendicular or non-perpendicular to the even or odd numbered lines. The freedom of two-dimensional patterning compared to conventional self-aligned multiple patterning (SAMP) processes used in the 1-D patterning processes is provided. The two-dimensional patterning described herein provides line widths that match the critical dimensions in both x and y directions. The separation between the 1-D lines or between 2-D interconnects and the end of 1-D lines can be kept to a constant and at a minimum.

Abstract: A transfer film providing a textured finish to the surface of a glass object comprises a color ink layer, a texture layer attached to a surface of the ink layer, a metal layer attached to a surface of the texture layer opposite from and contacting the ink layer, and an adhesive layer attached to a surface of the metal layer opposite from and contacting the texture layer. A transfer sticker and a glass product using the transfer film are also provided.

Abstract: A memory device is disclosed. The memory device comprises N flash memories and a flash manager. The flash manager comprises an interleave/de-interleave buffer and an addressing circuit. The interleave/de-interleave buffer operates according to a mode signal. The addressing circuit sequentially converts N input address signals to transmit N converted address signals. For write operations, the interleave/de-interleave buffer interleaves a write parameter stream into N interleaved streams according to the mode signal indicative of interleave mode and the N interleaved streams in conjunction with the N converted address signals are written into the N flash memories in parallel. For read operations, N read streams are read from the N flash memories in parallel in response to the N converted address signals and the interleave/de-interleave buffer de-interleaves the N read streams into a de-interleaved parameter stream according to the mode signal indicative of de-interleave mode.

Abstract: A method of fabricating three-dimensional patterns on a workpiece includes steps of providing a transparent film and forming a three-dimensional patterns on the transparent film. A layer of adhesive is coated on the three-dimensional patterns. A heat transfer film is used in transferring the three-dimensional patterns from the heat transfer film to a main surface of the workpiece using a vacuum heat transfer printing method.

Abstract: A fan control apparatus used to control a plurality of fans, and the fan control apparatus includes a power port, a control unit, a drive unit, and a trigger switch. The control unit receives a PWM signal with a duty cycle outputted from a processor and the control unit determines whether the duty cycle is greater than at least one threshold value set by the control unit. When the duty cycle is greater than at least one threshold value, the control unit controls the fans through the drive unit.