Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: A method for matrix by vector multiplication, applied in an artificial neural network system, is disclosed. The method comprises: compressing a plurality of weight values in a weight matrix and indices of an input vector into a compressed main stream; storing M sets of synapse values in M memory devices; and, performing reading and MAC operations according to the M sets of synapse values and the compressed main stream to obtain a number M of output vectors. The step of compressing comprises: dividing the weight matrix into a plurality of N×L blocks; converting entries of a target block and corresponding indices of the input vector into a working block and an index matrix; removing zero entries in the working block; shifting non-zero entries row-by-row to one of their left and right sides in the working block; and, respectively shifting corresponding entries in the index matrix.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

Abstract: There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: A water-cooling thermal dissipating system includes an electronic device and a thermal dissipating device. The electronic device includes a computing module includes a computing unit releasing heat when operation. The thermal dissipating device includes a thermal conducting unit, a pump, a tank, a thermal exchanger, and a controlling module; the thermal conductive unit is attached to the computing unit for thermal conduction; the pump is coupled to the thermal conductive unit, the pump, the tank, and the thermal exchanger for pumping a cooling-liquid therethrough, such that the cooling liquid is allowed to flow into the thermal conductive unit for absorbing heat. The controlling module generates an abnormal signal when the thermal dissipating device is sensed to be in an abnormal state, and the computing module forces to shut down the electronic device after continually receiving the abnormal signal for a predetermined time.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

Abstract: A fan control apparatus used to control a plurality of fans, and the fan control apparatus includes a power port, a control unit, a drive unit, and a trigger switch. The control unit receives a PWM signal with a duty cycle outputted from a processor and the control unit determines whether the duty cycle is greater than at least one threshold value set by the control unit. When the duty cycle is greater than at least one threshold value, the control unit controls the fans through the drive unit.

Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: A water-cooling thermal dissipating system includes an electronic device and a thermal dissipating device. The electronic device includes a computing module includes a computing unit releasing heat when operation. The thermal dissipating device includes a thermal conducting unit, a pump, a tank, a thermal exchanger, and a controlling module; the thermal conductive unit is attached to the computing unit for thermal conduction; the pump is coupled to the thermal conductive unit, the pump, the tank, and the thermal exchanger for pumping a cooling-liquid therethrough, such that the cooling liquid is allowed to flow into the thermal conductive unit for absorbing heat. The controlling module generates an abnormal signal when the thermal dissipating device is sensed to be in an abnormal state, and the computing module forces to shut down the electronic device after continually receiving the abnormal signal for a predetermined time.

Abstract: A method of manufacturing a piezoelectric element includes: forming a patterned mask layer over a substrate, in which the patterned mask layer has an opening exposing a portion of the substrate; forming a piezoelectric element in the opening; and removing the patterned mask layer to obtain the piezoelectric element, in which the piezoelectric element has a central portion and a peripheral portion adjacent to the central portion, and the peripheral portion has a maximum height greater than a height of the central portion.

Abstract: A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer with a hole over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer and forming a first mask element with a trench opening over the second dielectric layer. The method further includes forming a second mask element over the first mask element, and the second mask element has a via opening. In addition, the method includes etching the second dielectric layer through the via opening and etching the second dielectric layer through the trench opening. As a result, a trench and a via hole are formed in the second dielectric layer and the first dielectric layer, respectively. The method includes forming a conductive material in the via hole and the trench.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.