Patents by Inventor Chen-Hua Tsai
Chen-Hua Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079381Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: Chen-Hua YU, An-Jhih SU, Jing-Cheng LIN, Po-Hao TSAI
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Patent number: 11923315Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.Type: GrantFiled: July 12, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
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Patent number: 11923349Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.Type: GrantFiled: June 30, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Publication number: 20230330803Abstract: Systems and methods are provided for predicting irregular motions of one or more mechanical components of a semiconductor processing apparatus. A mechanical motion irregular prediction system includes one or more motion sensors that sense motion-related parameters associated with at least one mechanical component of a semiconductor processing apparatus. The one or more motion sensors output sensing signals based on the sensed motion-related parameters. Defect prediction circuitry predicts an irregular motion of the at least one mechanical component based on the sensing signals.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Inventors: Chunhung Chen, Yu Chi Tsai, Chin Wei Chuang, Bo-An Chen, Sheng-Chen Wang, Chen-Hua Tsai
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Patent number: 11731232Abstract: Systems and methods are provided for predicting irregular motions of one or more mechanical components of a semiconductor processing apparatus. A mechanical motion irregular prediction system includes one or more motion sensors that sense motion-related parameters associated with at least one mechanical component of a semiconductor processing apparatus. The one or more motion sensors output sensing signals based on the sensed motion-related parameters. Defect prediction circuitry predicts an irregular motion of the at least one mechanical component based on the sensing signals.Type: GrantFiled: June 5, 2019Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chunhung Chen, Yu Chi Tsai, Chin Wei Chuang, Bo-An Chen, Sheng-Chen Wang, Chen-Hua Tsai
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Publication number: 20210288137Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
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Patent number: 11024703Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: GrantFiled: June 29, 2020Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
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Publication number: 20200328270Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
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Patent number: 10707315Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.Type: GrantFiled: April 22, 2019Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Henry Kwong, Chih-Yung Lin, Po-Nien Chen, Chen Hua Tsai
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Patent number: 10700160Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: GrantFiled: July 15, 2019Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
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Publication number: 20200130130Abstract: Systems and methods are provided for predicting irregular motions of one or more mechanical components of a semiconductor processing apparatus. A mechanical motion irregular prediction system includes one or more motion sensors that sense motion-related parameters associated with at least one mechanical component of a semiconductor processing apparatus. The one or more motion sensors output sensing signals based on the sensed motion-related parameters. Defect prediction circuitry predicts an irregular motion of the at least one mechanical component based on the sensing signals.Type: ApplicationFiled: June 5, 2019Publication date: April 30, 2020Inventors: Chunhung Chen, Yu Chi Tsai, Chin Wei Chuang, Bo-An Chen, Sheng-Chen Wang, Chen-Hua Tsai
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Publication number: 20190341445Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
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Patent number: 10411085Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: GrantFiled: May 12, 2017Date of Patent: September 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
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Publication number: 20190245050Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Henry Kwong, Chih-Yung Lin, Po-Nien Chen, Chen Hua Tsai
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Patent number: 10355071Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: GrantFiled: May 12, 2017Date of Patent: July 16, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chiun Lin, Po-Nien Chen, Chen Hua Tsai, Chih-Yung Lin
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Patent number: 10312334Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.Type: GrantFiled: April 29, 2016Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Henry Kwong, Chih-Yung Lin, Po-Nien Chen, Chen Hua Tsai
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Patent number: 10276568Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.Type: GrantFiled: February 27, 2018Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
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Publication number: 20180190754Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.Type: ApplicationFiled: May 12, 2017Publication date: July 5, 2018Inventors: Yu-Chiun LIN, Po-Nien CHEN, Chen Hua TSAI, Chih-Yung LIN
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Publication number: 20180190654Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao