Patents by Inventor Chen-Hua Tsai
Chen-Hua Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140042636Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.Type: ApplicationFiled: October 28, 2013Publication date: February 13, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Patent number: 8597860Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.Type: GrantFiled: May 20, 2011Date of Patent: December 3, 2013Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Patent number: 8592271Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: GrantFiled: May 16, 2013Date of Patent: November 26, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Patent number: 8569127Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.Type: GrantFiled: March 13, 2012Date of Patent: October 29, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Yang Chen, Chen-Hua Tsai, Shih-Fang Hong, Po-Chao Tsao, Ming-Te Wei
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Publication number: 20130252387Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Publication number: 20130241001Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Yang Chen, Chen-Hua Tsai, Shih-Fang Hong, Po-Chao Tsao, Ming-Te Wei
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Publication number: 20130234292Abstract: A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Inventors: Ming-Te Wei, Po-Chao Tsao, Chen-Hua Tsai, Chien-Yang Chen, Chia-Jui Liang, Ming-Tsung Chen
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Patent number: 8486587Abstract: A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value.Type: GrantFiled: December 20, 2011Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Chia-Wei Huang
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Publication number: 20130157178Abstract: A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Inventors: Chen-Hua Tsai, Chia-Wei Huang
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Patent number: 8466502Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: GrantFiled: March 24, 2011Date of Patent: June 18, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Publication number: 20130052781Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Shih-Hung Tsai, Chien-Ting Lin
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Publication number: 20130043506Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
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Publication number: 20120309199Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.Type: ApplicationFiled: August 26, 2011Publication date: December 6, 2012Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
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Publication number: 20120299099Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Publication number: 20120295187Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Publication number: 20120241868Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: ApplicationFiled: March 24, 2011Publication date: September 27, 2012Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Patent number: 8273642Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.Type: GrantFiled: October 4, 2010Date of Patent: September 25, 2012Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Po-Jui Liao, Tzu-Feng Kuo, Ching-I Li, Cheng-Tzung Tsai
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Publication number: 20120199849Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.Type: ApplicationFiled: April 13, 2012Publication date: August 9, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai
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Publication number: 20120199888Abstract: A fin field-effect transistor structure includes a silicon substrate, a fin channel, a gate insulator layer and a gate conductor layer. The fin channel is formed on a surface of the silicon substrate, wherein the fin channel has at least one slant surface. The gate insulator layer formed on the slant surface of the fin channel. The gate conductor layer formed on the gate insulator layer.Type: ApplicationFiled: February 2, 2012Publication date: August 9, 2012Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Chun-Hsien Lin
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Patent number: 8207523Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.Type: GrantFiled: April 26, 2006Date of Patent: June 26, 2012Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai