Patents by Inventor Chen-Hua Tsai
Chen-Hua Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947658Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.Type: GrantFiled: April 11, 2016Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
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Patent number: 9857677Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.Type: GrantFiled: January 12, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Patent number: 9831242Abstract: In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.Type: GrantFiled: April 1, 2016Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Wei Soong, Chih-Pin Tsao, Hou-Yu Chen, Chen Hua Tsai
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Publication number: 20170316943Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Henry Kwong, Chih-Yung Lin, Po-Nien Chen, Chen Hua Tsai
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Publication number: 20170125413Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.Type: ApplicationFiled: April 11, 2016Publication date: May 4, 2017Inventors: Yu-Sheng WU, Chen Hua TSAI, Hou-Yu CHEN, Chia-Wei SOONG, Chih-Pin TSAO
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Publication number: 20170125412Abstract: In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.Type: ApplicationFiled: April 1, 2016Publication date: May 4, 2017Inventors: Chia-Wei SOONG, Chih-Pin TSAO, Hou-Yu CHEN, Chen Hua TSAI
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Patent number: 9406805Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.Type: GrantFiled: June 25, 2015Date of Patent: August 2, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
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Patent number: 9385193Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.Type: GrantFiled: May 27, 2014Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Publication number: 20160126182Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.Type: ApplicationFiled: January 12, 2016Publication date: May 5, 2016Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Patent number: 9269649Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.Type: GrantFiled: October 28, 2013Date of Patent: February 23, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Patent number: 9245822Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.Type: GrantFiled: October 28, 2013Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang
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Publication number: 20150295090Abstract: A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
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Patent number: 9105660Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.Type: GrantFiled: August 17, 2011Date of Patent: August 11, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Rai-Min Huang, Sheng-Huei Dai, Chun-Hsien Lin
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Patent number: 8860181Abstract: A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.Type: GrantFiled: March 7, 2012Date of Patent: October 14, 2014Assignee: United Microelectronics Corp.Inventors: Ming-Te Wei, Po-Chao Tsao, Chen-Hua Tsai, Chien-Yang Chen, Chia-Jui Liang, Ming-Tsung Chen
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Publication number: 20140252482Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.Type: ApplicationFiled: May 27, 2014Publication date: September 11, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Patent number: 8828878Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.Type: GrantFiled: August 26, 2011Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
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Publication number: 20140225197Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.Type: ApplicationFiled: April 25, 2014Publication date: August 14, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Patent number: 8772860Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.Type: GrantFiled: May 26, 2011Date of Patent: July 8, 2014Assignee: United Microelectronics Corp.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Patent number: 8691651Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.Type: GrantFiled: August 25, 2011Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Shih-Hung Tsai, Chien-Ting Lin
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Publication number: 20140042640Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.Type: ApplicationFiled: October 28, 2013Publication date: February 13, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Jian-Cheng Chen, Chin-Yueh Tsai, Yao-Jen Fan, Heng-Kun Chen, Hsiang Yang