Patents by Inventor Chen-Lin Yang

Chen-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11323101
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 3, 2022
    Assignee: AIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Fu-An Wu, Yangsyu Lin, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang
  • Patent number: 11301148
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20210350845
    Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 11, 2021
    Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
  • Patent number: 11133039
    Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Yu-Hao Hsu
  • Publication number: 20210203312
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Inventors: Hao-I YANG, Fu-An WU, Yangsyu LIN, Chiting CHENG, Cheng Hung LEE, Chen-Lin YANG
  • Publication number: 20210200452
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • Patent number: 11049555
    Abstract: A memory device includes a plurality of bit lines, a plurality of word lines, and a memory cell array including a plurality of bit cells coupled to the bit lines and the word lines. Each of the bit cells is configured to present an initial logic state on the bit lines. A power supply terminal is coupled to the memory cell array. A controller is coupled to the word lines and the bit lines, and is configured to, during a RNG phase, precharge the bit lines to a second voltage level lower than a first voltage level, and determine the initial logic states of the plurality of bit cells to generate a random number. The first voltage level is a voltage level for operating the memory cell array during an SRAM phase.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
  • Patent number: 10951200
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
  • Patent number: 10949100
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 16, 2021
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20200195236
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
  • Patent number: 10685686
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Publication number: 20200118602
    Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Yu-Hao Hsu
  • Publication number: 20200081636
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • Patent number: 10574213
    Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
  • Publication number: 20200020363
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Patent number: 10510380
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Patent number: 10503421
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20190252008
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Patent number: 10340897
    Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
  • Patent number: 10304500
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu