Patents by Inventor Chen-Lin Yang
Chen-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10685686Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: GrantFiled: September 25, 2019Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Publication number: 20200118602Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.Type: ApplicationFiled: October 7, 2019Publication date: April 16, 2020Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Yu-Hao Hsu
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Publication number: 20200081636Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
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Patent number: 10574213Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.Type: GrantFiled: November 30, 2018Date of Patent: February 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Publication number: 20200020363Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10510380Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: GrantFiled: April 23, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10503421Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.Type: GrantFiled: March 28, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Publication number: 20190252008Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10340897Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.Type: GrantFiled: July 19, 2018Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Patent number: 10304500Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: GrantFiled: February 22, 2018Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10276232Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.Type: GrantFiled: January 3, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
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Publication number: 20190103858Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.Type: ApplicationFiled: November 30, 2018Publication date: April 4, 2019Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20190036513Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.Type: ApplicationFiled: July 19, 2018Publication date: January 31, 2019Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20190005990Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: February 22, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Publication number: 20190004718Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.Type: ApplicationFiled: March 28, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yu-Hao HSU, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Publication number: 20180342291Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.Type: ApplicationFiled: January 3, 2018Publication date: November 29, 2018Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
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Patent number: 9978443Abstract: A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data.Type: GrantFiled: January 13, 2016Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Lin Yang, Ming-Chien Tsai, Chung-Yi Wu, Cheng Hung Lee
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Patent number: 9685224Abstract: A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.Type: GrantFiled: May 15, 2015Date of Patent: June 20, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin Yang, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 9659603Abstract: A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.Type: GrantFiled: December 28, 2015Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee
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Publication number: 20170040042Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits.Type: ApplicationFiled: December 28, 2015Publication date: February 9, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee