Patents by Inventor Chen-Lin Yang
Chen-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8767494Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.Type: GrantFiled: June 11, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Lin Yang, Chung-Yi Wu, Yu-Hao Hsu
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Publication number: 20140092695Abstract: One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chung-Hsien Hua, Chung-Yi Wu, Chen-Lin Yang, Cheng Hung Lee
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Publication number: 20140036580Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin YANG, Kao-Cheng LIN, Chung-Hsien HUA
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Publication number: 20130329505Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Lin Yang, Chung-Yi Wu, Yu-Hao Hsu
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Patent number: 8441885Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.Type: GrantFiled: March 18, 2011Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Min Chan, Li-Wen Wang, Jihi-Yu Lin, Chen-Lin Yang, Shao-Yu Chou
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Publication number: 20130094308Abstract: A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Lin Yang, Wei Min Chan, Chung-Hsien Hua
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Patent number: 8391097Abstract: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.Type: GrantFiled: May 25, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Wei Min Chan, Yen-Huei Chen, Chen-Lin Yang, Hsiu-Hui Yang, Shao-Yu Chou
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Patent number: 8296705Abstract: A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device.Type: GrantFiled: January 7, 2010Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chen-Lin Yang
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Publication number: 20120236675Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.Type: ApplicationFiled: March 18, 2011Publication date: September 20, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Min Chan, Li-Wen Wang, Jihi-Yu Lin, Chen-Lin Yang, Shao-Yu Chou
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Patent number: 8213241Abstract: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.Type: GrantFiled: February 16, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chen-Lin Yang
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Publication number: 20120110530Abstract: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin YANG, Wei Min CHAN
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Patent number: 8077517Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.Type: GrantFiled: December 18, 2008Date of Patent: December 13, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wen Wang, Yen-Huei Chen, Chen-Lin Yang, Hsien-Yu Pan, Shao-Yu Chou, Hung-Jen Liao
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Publication number: 20110292754Abstract: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei Min Chan, Yen-Huei Chen, Chen-Lin Yang, Hsiu-Hui Yang, Shao-Yu Chou
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Publication number: 20110199850Abstract: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.Type: ApplicationFiled: February 16, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chen-Lin YANG
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Publication number: 20110055783Abstract: A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device.Type: ApplicationFiled: January 7, 2010Publication date: March 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chen-Lin YANG
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Publication number: 20100157692Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: Li-Wen Wang, Yen-Huei Chen, Chen-Lin Yang, Hsien-Yu Pan, Shao-Yu Chou, Hung-Jen Liao
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Patent number: 7467365Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.Type: GrantFiled: September 14, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: George H. Chang, Yi-Kan Cheng, Chen-Teng Fan, Chen-Lin Yang, Yung-Chin Hou, Chu-Ping James Wang
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Publication number: 20080072191Abstract: This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: George H. Chang, Yi-Kan Cheng, Chen-Teng Fan, Chen-Lin Yang, Yung-Chin Hou, Chu-Ping James Wang