Patents by Inventor Chen-Ming Huang

Chen-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10437706
    Abstract: The present invention provides a debugging system and method for an embedded device, including: an embedded device, including a processing unit and a memory unit, where the memory unit includes a staging area used to store debugging data; a mobile storage device, including a debugging data control unit and a storage unit; and a computer, electrically connected to the embedded device and the mobile storage device. The debugging data control unit transmits a debugging demand message to the embedded device by using the computer. The embedded device transmits the debugging data in the staging area back to the computer. The computer transmits the debugging data to the mobile storage device and stores the debugging data in the storage unit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 8, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Shi-Jie Zhang, Che-Yen Huang, Chen-Ming Chang
  • Publication number: 20190295925
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, CHIH-HUNG Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20190243190
    Abstract: A pixel array substrate includes a substrate, pixel units, and signal lines. Each pixel unit includes an active device, a first insulation layer, a common electrode, a second insulation layer, and a pixel electrode. The common electrode is disposed on the first insulation layer and has openings. The pixel electrode is disposed on the second insulation layer and overlapped with the common electrode. The pixel electrode is electrically connected to the active device. The signal lines are disposed on the substrate and electrically connected to the active device, respectively. The openings include at least one first opening, and an orthogonal projection of the at least one first opening on the substrate is located between orthogonal projections of the pixel electrodes on the substrate and orthogonal projections of the signal lines on the substrate. A display panel including the pixel array substrate is also provided.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 8, 2019
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Chen-De Lee, Chun-Ming Huang, Chih-Chuan Chen
  • Patent number: 10357867
    Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
  • Publication number: 20190219252
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Publication number: 20190221701
    Abstract: A solar cell includes a photoelectric conversion layer, a doped layer, a first passivation layer, a first TCO layer, a front electrode and a back electrode. The doped layer is disposed on the front surface of the photoelectric conversion layer. The first passivation layer is disposed on the doped layer, wherein the first passivation layer has a plurality of openings exposing a portion of the doped layer. The first TCO layer is disposed on the first passivation layer and in the openings, and directly contacts the exposed doped layer via the openings, wherein a ratio of an area of the openings to an area of the first TCO layer is between 0.01 and 0.5. The front electrode is disposed on the first TCO layer. The back electrode is disposed on the back surface of the photoelectric conversion layer.
    Type: Application
    Filed: January 15, 2018
    Publication date: July 18, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Chao-Cheng Lin, Chorng-Jye Huang, Chen-Cheng Lin, Chun-Heng Chen, Chen-Hsun Du, Chun-Ming Yeh, Jui-Chung Hsiao
  • Patent number: 10353372
    Abstract: The device includes a master module and a slave module. The master module includes a control unit for controlling overall operation of the master module, a power unit electrically for storing electricity to supply the master module, an electricity transmission unit for receiving electricity from the power unit and wirelessly transmitting the electricity; and a communication unit for communicating of the master module. The slave module is electrically connected to the master module and includes a control subunit for controlling overall operation of the slave module, a communication subunit for wirelessly communicating with the communication unit, an electricity reception unit for wirelessly receiving the electricity from the power unit of the master module, a storage unit for storing electricity from the electricity reception unit and supplying power to each unit of the slave module, and an electricity transmission subunit for wirelessly outward transmitting electricity of the storage unit.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: July 16, 2019
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chun-Ming Huang, Chen-Chia Chen, Chien-Ming Wu
  • Publication number: 20190203003
    Abstract: A resin composition is provided. The resin composition comprises the following components: (A) a halogen-free epoxy resin; (B) a hardener; and (C) a phosphorus-containing phenolic resin of the following formula (I): wherein m, n, 1, R1, and R2 are as defined in the specification.
    Type: Application
    Filed: June 15, 2018
    Publication date: July 4, 2019
    Inventors: CHIH-WEI LIAO, GUAN-SYUN TSENG, TSUNG-HSIEN LIN, JU-MING HUANG, CHEN-HUA YU
  • Publication number: 20190172753
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Application
    Filed: January 2, 2018
    Publication date: June 6, 2019
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10312146
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 4, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10312384
    Abstract: A solar cell is provided. The solar cell includes a Si substrate having a first surface and a second surface opposite to each other, an emitter, a first electrode, a doped region, a passivation layer, a doped polysilicon layer, a semiconductor layer, and a second electrode. The emitter is disposed on the first surface. The first electrode is disposed on the emitter. The doped region is disposed in the second surface. The passivation layer is disposed on the second surface. The doped polysilicon layer is disposed on the passivation layer, wherein a plurality of holes penetrates the doped polysilicon layer and the passivation layer and exposes a portion of the second surface. The semiconductor layer is disposed on the doped polysilicon layer and in the holes. The band gap of the semiconductor layer is greater than that of the Si substrate. The second electrode is disposed on the semiconductor layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Cheng Lin, Chien-Kai Peng, Chen-Cheng Lin, Chen-Hsun Du, Chorng-Jye Huang, Chun-Ming Yeh
  • Publication number: 20190148166
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: August 1, 2018
    Publication date: May 16, 2019
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10263004
    Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Publication number: 20190109146
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Publication number: 20190043870
    Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.
    Type: Application
    Filed: September 1, 2017
    Publication date: February 7, 2019
    Inventors: Josh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
  • Publication number: 20190019731
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20180269308
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10032675
    Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10008581
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang