Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

Abstract: The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Abstract: A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.

Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.