Abstract: A pressure sensitive electrochromic device at least comprises a first substrate and a second substrate disposed opposite; a pressure sensitive layer disposed on the first substrate; an electrochromic layer disposed on the pressure sensitive layer; and a third conductive layer disposed between the electrochromic layer and the second substrate. The pressure sensitive layer includes a first conductive layer disposed on the first substrate; an insulative layer in which numerous conductive grains are distributed; and a second conductive layer disposed on the insulative layer. Also, at least one of the first and second substrates is made of the flexible material. An external circuit is applied for connecting the first and third conductive layers.

Abstract: Bond pad structures and semiconductor devices using the same. An exemplary semiconductor device comprises a substrate. An intermediate structure is formed over the substrate. A bond pad structure is formed over the intermediate structure. In one exemplary embodiment, the intermediate structure comprises a first metal layer neighboring and supporting the bond pad structure and a plurality of second metal layers underlying the intermediate structure, wherein one of the second metal layers functions as a power line.

Abstract: A stapler includes a housing, a magazine, a guide plate, and a driving mechanism. The housing has a base with a driving end. The magazine is associated with the base and has a plurality of sidewalls defining a channel. The guide plate is connected to the base at the driving end and has a face oriented towards the magazine. An inner channel is formed within an outer channel along the face. The drive mechanism is disposed within the housing and has a driver with a free end. The driver slidably extends between a first position between the guide plate and the magazine and a second position in the housing.

Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Abstract: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Abstract: In one embodiment, the transmitters and detectors for an integrated optical touch panel (OTP) are mounted at right angles to the surface of the OTP. The transmitters and detectors are contained on a substrate which is an extension of the substrate containing the touch panel display itself. The sides of the substrate containing the transmitters and detectors are folded upward so that the transmitters and detectors are positioned above the plane of the substrate containing the display.

Abstract: A method of electroplating conductive material on semiconductor wafers improves deposited film quality by providing greater control over the formation of the film grain structure. Better grain size control is achieved by applying a continuous DC plating current to the wafer which avoids sharp discontinuities in the current as the applied current is increased in successive stages during a plating cycle. Current discontinuities are avoided by gradually increasing the current in a ramp-like fashion between the successive plating stages.

Abstract: The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Abstract: A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

Abstract: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Abstract: A light reflecting structure includes a light source and the at least one reflector. The reflector is disposed in the vicinity of the light source, and includes a plurality of reflecting regions and shading regions discretely arranged at a surface thereof to respectively reflect and shelter the light emitted from the light source, thereby generating a reflective light with substantially identical brightness.

Abstract: A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.

Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Abstract: A method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by applying F ions to the copper layer to form a buffer zone on a surface of the copper layer and in-situ depositing a capping layer overlying the copper layer. The F ions remove copper oxide naturally formed on the copper surface and the buffer zone transfers thermal vertical strain in the copper to horizontal strain thereby preventing formation of copper hillocks.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: An integrated circuit package having central leads comprises a substrate has an upper surface, a lower surface, and a long slot penetrating the upper surface to the lower surface. The lower surface is forming with wiring regions arranged at the two sides of the long slot, and the wiring regions are forming with a plurality of connected points. A glue layer is coated on the upper surface of the substrate and is arranged at the periphery of the long slot. The integrated circuit has a first surface forming with a plurality of bonding pads, which is adhered to the glue layer. The wires, each of which is arranged within the long slot of the substrate and is electrically connected the bonding pad of the integrated circuit to the connected point of the substrate; and The first compound layer is filled within the long slot of the substrate for protecting the each wire.

Abstract: An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

Abstract: An electropolishing device having: an electrode device, which includes a positive electrode guide, a negative electrode guide, a positive electrode plate, a negative electrode plate and a negative working electrode; a clamping apparatus, which includes at least an insulated screw, an upper insulated piece and a lower insulated piece; and an insulated structure, which includes an upper insulated cover and a lower insulated cover.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: The subject invention provides an intraocular lens comprising an optic lens body and a layer of a photocatalytic material coated on at least a portion of a surface of the optic lens body. The intraocular lens of the subject invention can eliminate endophthalmitis and inhibit after-cataracts following cataract surgery.