Patents by Inventor Chen-Shien Chen

Chen-Shien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833033
    Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Publication number: 20200350395
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chien-Chih KUO, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20200350782
    Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chen-Hua Yu, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng, Sen-Kuei Hsu, Yu-Feng Chen, Yen-Liang Lin
  • Publication number: 20200343162
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20200328169
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Publication number: 20200321431
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu KU, Chi-Cheng CHEN, Hon-Lin HUANG, Wei-Li HUANG, Chun-Yi WU, Chen-Shien CHEN
  • Publication number: 20200321326
    Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 10797005
    Abstract: A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface of the die, and a molding compound surrounding the die and the warpage control unit. The warpage control unit includes an adhesive portion disposed over the second surface of the die and a warpage adjustable portion sandwiched between the adhesive portion and the die.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Shien Chen, Ming-Da Cheng, Ming-Chih Yew, Yu-Tse Su
  • Patent number: 10784223
    Abstract: A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng
  • Publication number: 20200273827
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Application
    Filed: May 10, 2020
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 10756162
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an adhesive layer over a semiconductor substrate and forming a magnetic element over the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a conductive line over the isolation element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Chen, Wei-Li Huang, Chien-Chih Kuo, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Publication number: 20200266074
    Abstract: A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Wei Sen Chang, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
  • Patent number: 10748810
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10748785
    Abstract: A device includes a plurality of first pads in a package substrate, wherein at least one first pad is of a first elongated shape, a plurality of vias in a dielectric layer and over the plurality of first pads, and a plurality of second pads over the package substrate, wherein at least one second pad is of a second elongated shape, and wherein the plurality of second pads is over a top surface of the dielectric layer and placed in a first region, a second region, a third region and a fourth region, and wherein second pads in two contiguous regions are oriented in two different directions.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Patent number: 10741477
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20200251463
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 10734347
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10720487
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 10720788
    Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng, Sen-Kuei Hsu, Yu-Feng Chen, Yen-Liang Lin