Abstract: Conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: A method includes providing a library of hardware-agnostic packet-processing functions. A functional hardware-agnostic specification of a packet-processing pipeline is received from a user. The specification is defined in terms of one or more of the packet-processing functions drawn from the library. A hardware-specific design of the packet-processing pipeline, which is suited to given hardware, is derived from the specification.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: This document provides methods and materials for using low coverage whole genome sequencing techniques to assess genomes. For example, methods and materials for using targeted nucleic acid amplification and/or capture techniques in combination with low coverage whole genome sequencing techniques to obtain high coverage sequencing data for one or more pre-selected regions of a genome are provided.

Abstract: A fingerprint identification module provided by the present disclosure includes a fingerprint identification panel provided with a fingerprint identification region; a middle shell including a partition plate and a middle frame, where the partition plate is at a side opposite a fingerprint identification side of the fingerprint identification panel, the partition plate is detachably connected to the middle frame, and the middle frame includes an accommodation space, the accommodation space being internally provided with the partition plate and the fingerprint identification panel; and a main board in the accommodation space, the main board being at a side, far away from the fingerprint identification panel, of the partition plate, and the main board being electrically connected to the fingerprint identification panel.

Abstract: A metal oxide thin film transistor is provided, which includes a metal oxide semiconductor layer, including a first semiconductor layer and a second semiconductor layer, the carrier mobility of the first semiconductor layer is higher than that of the second semiconductor layer; the metal oxide semiconductor layer includes a lower surface, an upper surface and a lateral surface, the source electrode is in contact with the lateral surface and the upper surface; the region where the lateral surface contacts the source electrode or the drain electrode includes a first contact region and a second contact region; which have the shape: a first angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the first contact region is larger than a second angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the second contact region.

Abstract: A cover, a fluid end and a plunger pump are provided. The cover includes: a body, the body being cylindrical, and the body including a first end, a second end, and a side surface connecting the first end and the second end; a main flow channel extending along an axis of the body; a plurality of subsidiary flow channels, each of the plurality of subsidiary flow channels being communicated with the main flow channel; a first opening, located at the first end and communicated with the main flow channel; and a plurality of second openings, located at the side surface of the body; each of the plurality of subsidiary flow channels being communicated with at least one of the plurality of second openings.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: Systems, methods, and apparatuses provide a scalable framework for analyzing queuing and transient congestion in network switches. The system reports which flows contributed to the queue buildup and enables direct per-packet action in the data plane to prevent transient congestion. The system may be configured to analyze queuing in legacy network switches.

Abstract: An aluminum battery negative electrode structure includes an aluminum foil and a coating layer. The coating layer is arranged on the aluminum foil. A material of the coating layer includes a high specific surface area carbon material. A specific surface area of the high specific surface area carbon material ranges from 500 m2/g to 3,000 m2/g.

Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal ?. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.

Abstract: A method of two-stage sidelink control information (SCI) can include receiving a transport block, and transmitting from a transmission user equipment (Tx UE) to a reception user equipment (Rx UE) the transport block with two-stage SCI including a 1st-stage SCI and a 2nd-stage SCI. The 1st-stage SCI can be transmitted over a physical sidelink control channel (PSCCH). The 2nd-stage SCI and the transport block can share resources of a physical sidelink shared channel (PSSCH). The 2nd-stage SCI and the transport block can share a demodulation reference signal (DMRS).

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: A method of configuring a PUSCH repetition and a UE using the same method are provided. The method includes: obtaining a plurality of invalid symbol patterns; and performing a plurality of PUSCH repetition transmissions according to the plurality of invalid symbol patterns.

Abstract: A method of two-stage sidelink control information (SCI) for sidelink transmission is described. In one novel aspect, the SCI is transmitted from a transmission UE (Tx UE) to a reception UE (Rx UE) in two stages. In one embodiment, the 1st-stage SCI carries information related to channel sensing, and is transmitted over a physical sidelink control channel (PSCCH). The 2nd-stage SCI is transmitted over a physical sidelink shared channel (PSSCH) associated with the PSCCH. In one embodiment, the first-stage SCI includes priority information or information of time-frequency resources for the SL transmission. In another embodiment, the first-stage SCI indicates time-frequency location of the second-stage SCI.

Abstract: The present disclosure provides an information processing method and apparatus, a terminal, and a storage medium. The information processing method comprises: receiving input topic information and sending the topic information to a server; displaying the topic information in a preset topic format on a session interface of a session group, the preset topic format having a reply area; receiving reply information used for replying to the topic information; and displaying the reply information in the reply area of the topic information. According to the method of the present disclosure, information is displayed in the form of topic information and reply information, and reply information corresponding to the same topic is displayed corresponding to the same topic information, such that the display mode of information is more reasonable, and a user can conveniently and quickly find information of interest.

Abstract: A system for display and interaction includes an interface and a processor. The interface is configured to receive data from one or more sensors. The processor is configured to convert the data to a common synthetic data space; provide the common synthetic data space for display; receive a command associated with an object represented in the common synthetic data space; and cause display of an icon indicating a command has been issued.

Abstract: A heterojunction cell and a method for preparing same. The heterojunction cell comprises: a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises: a bottom intrinsic layer; and a wide-band-gap intrinsic layer, which is located on the surface of the side of the bottom intrinsic layer that is away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer being greater than the band gap of the bottom intrinsic layer. The band gap of a wide-band-gap intrinsic layer is larger, and when sunlight irradiates a heterojunction cell, photons, the energy of which is less than that of the band gap of the wide-band-gap intrinsic layer, cannot be subjected to parasitic absorption.

Abstract: Embodiments of present invention provide a method of taking photo in a virtual reality environment. The method includes defining a group that includes multiple entities; detecting multiple directions that the multiple entities are facing based upon orientations of the multiple entities; identifying multiple extension lines that start from the multiple entities in the group and extend in the multiple directions; identifying one or more intersections associated with the multiple directions; identifying one or more connection lines that connect a center of the group to the one or more intersections; defining a camera line based on the one or more connection lines; determining a camera location along the camera line; taking an image of virtual view of the multiple entities by a virtual camera; and providing the image as a photo to the multiple entities in the group. A non-transitory storage medium and a computing environment are also provided.