Abstract: A display panel and a display device are provided. The display panel includes a base substrate, a plurality of pixel drive circuit units, n first signal lines, a touch layer, and a light emitting element. A distance between first extending portions of two adjacent first signal lines is greater than a distance between first bending portions of the two adjacent first signal lines. An orthogonal projection overlap area between the first connecting portion and first extending portions of the n first signal lines is S1, and an orthogonal projection overlap area between the first connecting portion and first bending portions of the n first signal lines is S2. S1?S2. A length of a first extending portion of at least one first signal line is L1, a distance between the first extending portion of at least one first signal line and the second electrode is H1, and H1?(S1/n)/L1.

Abstract: A display panel and a display device are provided. The display panel includes a first color sub-pixels and a second color sub-pixel. The first color sub-pixel includes a first effective light emitting region, the second color sub-pixel includes a second effective light emitting region, an area of the second effective light emitting region is smaller than that of the first effective light emitting region. The first color sub-pixel includes a first color light emitting layer, the second color sub-pixel includes a second color light emitting layer, an area ratio between orthographic projections of the first color light emitting layer and the first effective light emitting region on the base substrate is less than an area ratio between orthographic projections of the second color light emitting layer and the second effective light emitting region on the base substrate.

Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, and a gate scan driving circuit, a light-emitting control scan driving circuit, and a first power line, the gate scan driving circuit includes a first stabilizing capacitor, a first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scan driving circuit; and the light-emitting control scan driving circuit includes a second stabilizing capacitor, a first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal, a second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, the second electrode plate of the second stabilizing capacitor includes a first part and a second part, and an organic insulation layer is provided between the first part and the second part.

Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

Abstract: A torque transmission member for transmitting torque between a first rotating member and a second rotating member is provided. The torque transmission member has a first connection part and a second connection part which are concentrically arranged and fixedly connected with each other, wherein the first connection part is fixedly connected to the first rotating member, the second connection part is connected to the second rotating member in a torsion-proof manner, and the second connection part has a central hole for receiving the second rotating member. A cylindrical centering reference member is provided, the torque transmission member and the centering reference member are coaxially arranged by a centering tool during the process of assembling the torque transmission member, wherein the first connection part is provided with at least two through holes, and the centering tool passes through the through holes during a process of centering.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel has a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes: an array layer on a base substrate and a light shielding layer on a side of the array layer away from the base substrate, wherein the array layer includes a driving transistor and a switching transistor, the switching transistor is a transistor connected to a gate electrode of the driving transistor, a plurality of imaging pinholes are formed in the light shielding layer, and a first orthographic projection of the imaging pinholes onto the base substrate and a second orthographic projection of an active layer pattern of the switching transistor in the array layer onto the base substrate do not overlap at least in part.

Abstract: Embodiments of this application provide an information processing method and a coding apparatus. An information bit sequence includes a K-bit information block. The information bit sequence is to be processed into an encoded bit sequence with a target code length M. For a given code rate R, when the length K of the information block is greater than a preset threshold, the information bit sequence is segmented into two or more segments. Each segment is polar encoded into an encoded subsequence. The encoded subsequence has a length that equals to a mother code length Ni, and i=1, 2, . . . , p. Each of the p encoded subsequences is rate matched to obtain a rate-matched encoded subsequence. A rate-matched encoded subsequence i of the p rate-matched encoded subsequences has a code length Mi. The p rate-matched encoded subsequences are concatenated into an encoded bit sequence which has a code length M.

Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

Abstract: A magnetic recording medium includes a substrate, an underlayer provided on the substrate, and a magnetic layer provided on the underlayer and having a L10 structure and a (001) orientation. The magnetic layer has a granular structure in which an organic compound having a methylene skeleton or a methine skeleton is arranged at grain boundaries of magnetic grains.

Abstract: A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.

Abstract: A pixel driving circuit, a display device and an electronic device are provided. The pixel driving circuit includes: a first sub-pixel driving circuit, a second sub-pixel driving circuit, a third sub-pixel driving circuit, and a fourth sub-pixel driving circuit sequentially arranged in a first direction; a detection line; a first power line extending in the second direction; and a second power line extending in the second direction; wherein one of the first power line and the second power line is provided on a side of the second sub-pixel driving circuit away from the third sub-pixel driving circuit, and the other of the first power line and the second power line is provided on a side of the third sub-pixel driving circuit away from the second sub-pixel driving circuit.

Abstract: Provided are a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes multiple sub-pixels, wherein each sub-pixel includes a light-emitting region and a non-light-emitting region, and each sub-pixel is provided with a drive circuit; the drive circuit includes a storage capacitor and multiple transistors; for each sub-pixel, the multiple transistors are in the non-light-emitting region, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on a base substrate coincides with the light-emitting region. A first electrode of the storage capacitor is disposed in a same layer as an active layer of the multiple transistors, but in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is on a side of the first electrode close to the base substrate.

Abstract: According to a scheduling method and apparatus in a communication system, and a storage medium, a communication device obtains system status information, where the system status information includes network status information; obtains a scheduling policy based on the system status information and a deep neural network; and performs communication according to the scheduling policy. The deep neural network is obtained through training based on historical system status information, and the historical system status information includes system status information in all scheduling periods before a current scheduling period. Therefore, the scheduling policy obtained based on the deep neural network can meet a balancing requirement of throughput and fairness and solves a problem of low performance of an existing communication system.

Abstract: A display panel and a display device. The display panel includes a pixel circuit structure, a data line and a voltage signal line. The data line is connected to the pixel circuit structure to provide a data signal; the voltage signal line is connected to the pixel circuit structure to provide a voltage signal, the voltage signal is a constant voltage signal; the pixel circuit structure includes a first stabilization capacitor provided between the data line and the voltage signal line.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance.

Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.

Abstract: Disclosed are an array substrate, a display panel and a display device. The display panel includes a plurality of sub-pixel regions; each of the sub-pixel regions includes a pixel driving circuit, a white electroluminescent device connected with the pixel driving circuit and a color resist layer corresponding to the sub-pixel region; the plurality of sub-pixel regions include a first-color sub-pixel region, a second-color sub-pixel region and a third-color sub-pixel region; a width-to-length ratio of a channel region of the driving transistor in the first-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the second-color sub-pixel region, and the width-to-length ratio of the channel region of the driving transistor in the second-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the third-color sub-pixel region.

Abstract: The present invention discloses a CRISPR/LpCas9 gene editing system and application thereof, the CRISPR/LpCas9 gene editing system includes a complex of LpCas9 protein and sgRNA, which can accurately locate a target DNA sequence and cleave DNA double strands. The LpCas9 protein has an amino acid sequence shown in SEQ ID NO:1; and the sgRNA has a nucleotide sequence shown in SEQ ID NO:2, or a modified sgRNA sequence based on SEQ ID NO: 2. The present invention can effectively solve the problems of heterologous codon bias and cytotoxicity in the application of SpCas9 in Lactobacillus paracasei. The gene editing is performed in cells or in vitro by introducing artificially designed CRISPR RNA and a repair template, which solves the problem of low electroporation efficiency caused by the strains' characteristics or relatively large carried plasmids, and has broad application prospects in the field of gene editing.