Abstract: This application provides an encoding method and apparatus in wireless communications between a network device and a terminal. The method includes: performing cyclic redundancy check (CRC) encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits, L=11; and performing polar encoding on the first bit sequence.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.

Abstract: The present disclosure relates to a shift register for a display panel. The shift register may include an input terminal, an output terminal, an input unit, an output unit, a first control unit, a second control unit, and a first isolation unit. The output unit may be configured to transmit a first level or a second level to an output terminal based on levels of a first node and a second node.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

Abstract: A magnetic recording medium includes a magnesium oxide underlayer including magnesium oxide, and a magnetic layer including an alloy having a L10 structure and includes Fe or Co and Pt. The magnesium oxide has a peak of an O1s spectrum detected in a range of 531 eV to 533 eV when measured by X-ray photoelectron spectroscopy.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: The present disclosure is directed to pulverulent thermoplastic polymer blends comminuted to a particle size of less than 300 ?m. The pulverulent thermoplastic polymer blends can include a first thermoplastic polyurethane and a second thermoplastic polyurethane at a weight ratio of from about 90:10 to about 30:70 first thermoplastic polyurethane to second thermoplastic polyurethane. The first thermoplastic polyurethane can include a reaction product of a first reaction mixture consisting of or consisting essentially of an aliphatic diisocyanate having a number average molecular weight of from 140 g/mol to 170 g/mol and an aliphatic diol having a number average molecular weight of from 62 g/mol to 120 g/mol.

Abstract: The disclosure provides a display panel and a display device. The display panel includes: a base substrate, a transistor array layer, a pixel defining layer, touch electrodes. The area of opening region of first color sub-pixel is smaller than that of opening region of third color sub-pixel, the area of opening region of second color sub-pixel is smaller than that of opening region of third color sub-pixel. An orthogonal projection of second capacitor in first color sub-pixel and an orthogonal projection of touch electrodes have a first auxiliary overlap area, an orthogonal projection of second capacitor in second color sub-pixel and orthogonal projection of the touch electrodes have a second auxiliary overlap area, an orthogonal projection of second capacitor in third color sub-pixel and orthogonal projection of touch electrodes have a third auxiliary overlap area. The first and/or second auxiliary overlap area is larger than the third auxiliary overlap area.

Abstract: The present disclosure is directed to thermoplastic polymer blends. The blends can include a first thermoplastic polyurethane and a second thermoplastic polyurethane, wherein the blend includes from 10 wt % to 50 wt % of the second thermoplastic polyurethane based on a total weight of the thermoplastic polymer blend. The first thermoplastic polyurethane can include a reaction product of a first reaction mixture consisting of or consisting essentially of an aliphatic diisocyanate and an aliphatic isocyanate-reactive component. The second thermoplastic polyurethane can include a reaction product of a second reaction mixture including a polyisocyanate, an isocyanate-reactive component having a number average molecular weight of from 500 g/mol to 10,000 g/mol, and a chain extender having a number average molecular weight of from 60 g/mol to 450 g/mol.

Abstract: A magnetic recording medium includes a substrate, an underlayer provided on the substrate and including MgO, and a magnetic layer provided on the underlayer and including an alloy having a L10 crystal structure. The magnetic layer includes first, second, and third magnetic recording layers successively provided in this order above the underlayer. A Curie temperature of the second magnetic recording layer is lower than a Curie temperature of each of the first and third magnetic recording layers, by a value which falls within a range of 30 K to 100 K. An average grain diameter of magnetic grains at a bottom surface portion of the first magnetic recording layer is smaller by 15% or more than average grain diameters of magnetic grains at bottom surface portions of the second and third magnetic recording layers.

Abstract: A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, a first power line and an electrical connection layer on the base substrate. Each sub-pixel includes a pixel circuit, and a plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns along a first direction and a second direction. The sub-pixel is electrically connected with the light-emitting element through the electrical connection layer, and the portion, which is in the display region of the display substrate, of the electrical connection layer is not overlapped with the first power line in a direction perpendicular to the base substrate.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: Provided are a control method and a device for active power of a wind power plant cluster. The wind power plant cluster includes wind power plants of m priorities, wherein m is a positive integer. The control method includes: monitoring the consumption capability of a power grid in real time, and determining object active power of the wind power plant cluster according to the consumption capability of the power grid; determining a command active power of the wind power plant within each priority according to the object active power of the wind power plant cluster in a descending order of the priorities; and controlling real active power of the wind power plant within each priority according to the command active power.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate, and the pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode, a first electrode, and a second electrode; the first transistor includes a first active region, the second transistor includes a second active region, the driving transistor includes a fourth active region, at least one of a doping concentration of the first active region and a doping concentration of the second active region is greater than a doping concentration of the fourth active region.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel has a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: A data processing method and a data processing apparatus are provided to reduce a bit error rate of a wireless communications system and improve transmission performance of the wireless communications system. The method includes: mapping L to-be-sent bits to L bit locations included in at least one modulation symbol, where the L to-be-sent bits include at least one bit field, a bit in a bit field having a high priority is preferentially mapped to a bit location that is of the at least one modulation symbol and that has a high reliability level, the at least one bit field is at least one of an information bit field, a first parity bit field, and a second parity bit field; and outputting the at least one modulation symbol.

Abstract: The present invention relates to a package structure and package method for a cavity device group. The package structure includes a substrate, the substrate including a first substrate surface and a second substrate surface which face each other, wherein a first cavity device group is provided on the first substrate surface. The package structure further includes: a first sealing layer encapsulating the first cavity device group; and a first plastic package layer encapsulating the first sealing layer, wherein the flowability of a sealing material of the first sealing layer is less than that of a plastic package material of the first plastic package layer. The problems of device damage and functional failure of a cavity device group in the existing package structure because it is likely affected by a mold flow pressure in the injection molding process can be solved, while the function and miniaturization of a module are maintained.

Abstract: A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.